Cypress CY7C1387D - Manuals

Cypress CY7C1387D – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1387D

Summary

Page 3 - Pin Configurations

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 3 of 30 Pin Configurations A A A A A 1 A 0 NC/7 2 M NC/3 6 M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ ...

Page 5 - TMS

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386D (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C ...

Page 6 - Pin Definitions

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 6 of 30 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , C...

Page 9 - Truth Table

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 9 of 30 Truth Table [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L...

Page 11 - Disabling the JTAG Feature; TAP Controller State Diagram; TAP Controller Block; TAP Controller Block Diagram; Performing a TAP Reset; TAP Registers; Instruction Register

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 11 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using J...

Page 12 - Identification Register; TAP Instruction Set; Identification

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 12 of 30 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To...

Page 13 - Reserved; TAP Timing

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 13 of 30 the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. Wh...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 14 of 30 3.3V TAP AC Test Conditions Input pulse levels .................................................V SS to 3.3V Input rise and fall times .................................................. 1 nsInput timing referen...

Page 16 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 16 of 30 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 ...

Page 17 - 65-Ball BGA Boundary Scan Order

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 17 of 30 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3...

Page 18 - Electrical Characteristics

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 18 of 30 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature w...

Page 20 - Switching Characteristics

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 20 of 30 Switching Characteristics Over the Operating Range [20, 21] Parameter Description –250 –200 –167 Unit Min Max Min Max Min Max t POWER V DD (Typical) to the First Access [22] 1 1 1 ms Clock t CYC Clock Cycle Tim...

Page 21 - Switching Waveforms; Read Cycle Timing

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 21 of 30 Switching Waveforms Read Cycle Timing [26] tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES GW, BWE,BW Data Out (DQ) High-Z tDOH tCO ADV t OEHZ t CO Single READ BURST READ tOEV t OELZ t C...

Page 22 - Write Cycle Timing

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 22 of 30 Write Cycle Timing [26, 27] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A3) D(A3 + 1) D(A2 + 3...

Page 23 - Read/Write Cycle Timing

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 23 of 30 Read/Write Cycle Timing [26, 28, 29] Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data ...

Page 24 - ZZ Mode Timing; CLK

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 24 of 30 ZZ Mode Timing [30, 31] Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30. Device must be desel...

Page 25 - Ordering Information; for actual products offered.

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 25 of 30 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Orderin...

Page 27 - Package Diagrams

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 27 of 30 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END...

Page 30 - Document History Page; SRAM

CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 30 of 30 Document History Page Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM Document Number: 38-05545 REV. ECN NO. Issue Date Orig. of Change Descripti...