Cypress CY7C1381DV25 - Manuals

Cypress CY7C1381DV25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1381DV25

Summary

Page 3 - Pin Configurations

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 3 of 28 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ...

Page 5 - TMS

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 5 of 28 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381DV25 (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A ...

Page 6 - Pin Definitions

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 6 of 28 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and C...

Page 7 - Functional Overview; Truth Table

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 7 of 28 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133 MHz device). The CY7C1381...

Page 8 - Interleaved Burst Address Table; DD; ZZ Mode Electrical Characteristics

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 8 of 28 and the IOs must be tri-stated prior to the presentation of datato DQs. As a safety precaution, the data lines are tri-statedonce a write cycle is detected, regardless of the state of OE. Single Write Acc...

Page 11 - Disabling the JTAG Feature; TAP Controller State Diagram; Performing a TAP Reset; TAP Registers; Instruction Register

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 11 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381DV25/CY7C1383DV25 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-st...

Page 12 - Identification Register; TAP Instruction Set; Identification

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 12 of 28 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board level serial test data path. Bypass Regi...

Page 13 - Reserved; TAP Timing

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 13 of 28 the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output ...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 14 of 28 2.5V TAP AC Test Conditions Input pulse levels .................................................V SS to 2.5V Input rise and fall time..................................................... 1 nsInput timing...

Page 16 - 65-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 16 of 28 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A...

Page 17 - Electrical Characteristics

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 17 of 28 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temper...

Page 19 - Switching Characteristics

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 19 of 28 Switching Characteristics Over the Operating Range [19, 20] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (Typical) to the first Access [21] 1 1 ms Clock t CYC Clock Cycle T...

Page 20 - Timing Diagrams; Read Cycle Timing

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 20 of 28 Timing Diagrams Read Cycle Timing [25] tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t CEH tCES Data Out (Q) High-Z t CLZ tDOH tCDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps ar...

Page 21 - Write Cycle Timing

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 21 of 28 Write Cycle Timing [25, 26] Timing Diagrams (continued) t CYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) ...

Page 22 - Read/Write Cycle Timing

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 22 of 28 Read/Write Cycle Timing [25, 27, 28] Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1...

Page 23 - ZZ Mode Timing; CLK

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 23 of 28 ZZ Mode Timing [29, 30] Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 29. Device must be de...

Page 24 - Ordering Information; for actual products offered.

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 24 of 28 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 25 - Package Diagrams

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 25 of 28 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUS...

Page 28 - Document History Page; Change

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 28 of 28 Document History Page Document Title: CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/CY7C1383FV25, 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05547 REV. ECN NO. Issue Date Orig. of Change ...