Cypress CY7C1381D - Manuals

Cypress CY7C1381D – Manual in PDF format online.

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Manual

Manual Cypress CY7C1381D

Summary

Page 3 - Pin Configurations

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 3 of 29 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A D...

Page 5 - TMS

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 5 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381D (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D ...

Page 6 - Pin Definitions

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 6 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 ,...

Page 7 - Functional Overview; Truth Table

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 7 of 29 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133 MHz device). The CY7C1381D/CY7C1383D/...

Page 8 - Interleaved Burst Address Table; DD; ZZ Mode Electrical Characteristics

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 8 of 29 deasserted and the IOs must be tri-stated prior to the presen-tation of data to DQs. As a safety precaution, the data lines aretri-stated once a write cycle is detected, regardless of the stateof OE. Single Write Acc...

Page 11 - Disabling the JTAG Feature; TAP Controller State Diagram; TAP Controller Block; TAP Controller Block Diagram; Performing a TAP Reset; TAP Registers; Instruction Register

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 11 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-s...

Page 12 - Identification Register; TAP Instruction Set; Identification

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 12 of 29 Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO...

Page 13 - Reserved; TAP Timing

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 13 of 29 (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This b...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 14 of 29 3.3V TAP AC Test Conditions Input pulse levels .................................................V SS to 3.3V Input rise and fall times ................................................... 1 nsInput timing reference l...

Page 16 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 16 of 29 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 ...

Page 17 - 65-Ball BGA Boundary Scan Order

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 17 of 29 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9...

Page 18 - Electrical Characteristics

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 18 of 29 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with P...

Page 20 - Switching Characteristics

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 20 of 29 Switching Characteristics Over the Operating Range [20, 21] Parameter Description 133 MHz 100 MHz Unit Min Max Min Max t POWER V DD (Typical) to the first Access [22] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t ...

Page 21 - Timing Diagrams; Read Cycle Timing

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 21 of 29 Timing Diagrams Read Cycle Timing [26] tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t CEH tCES Data Out (Q) High-Z t CLZ tDOH tCDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps aroundto its i...

Page 22 - Write Cycle Timing

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 22 of 29 Write Cycle Timing [26, 27] Timing Diagrams (continued) t CYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2...

Page 23 - Read/Write Cycle Timing

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 23 of 29 Read/Write Cycle Timing [26, 28, 29] Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(...

Page 24 - ZZ Mode Timing

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 24 of 29 ZZ Mode Timing [30, 31] Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 30. Device must be deselected wh...

Page 25 - Ordering Information; for actual products offered.

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 25 of 29 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative orvisit www.cypress.com for actual products offered. Speed (MHz) Ordering Code ...

Page 26 - Package Diagrams

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLAS...

Page 29 - Document History Page; Change

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev. *F Page 29 of 29 Document History Page Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05544 REV. ECN NO. Issue Date Orig. of Change Description of Change ** ...