Cypress CY7C1380DV25 - Manuals

Cypress CY7C1380DV25 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1380DV25

Summary

Page 3 - Pin Configurations

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 3 of 29 Pin Configurations A A A A A 1 A 0 NC/ 72M NC/ 36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V ...

Page 5 - TMS

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 5 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1380DV25 (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A C...

Page 6 - Pin Definitions

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 6 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE...

Page 8 - Linear Burst Address Table

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 8 of 29 ADSP triggered write accesses require two clock cycles tocomplete. If GW is asserted LOW on the second clock rise, thedata presented to the DQs inputs is written into thecorresponding address location in t...

Page 9 - Truth Table

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 9 of 29 Truth Table [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X...

Page 11 - Disabling the JTAG Feature; TAP Controller State Diagram; Performing a TAP Reset; TAP Registers; Instruction Register

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 11 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380DV25/CY7C1382DV25 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-sta...

Page 12 - Identification Register; TAP Instruction Set; Identification

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 12 of 29 Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the ...

Page 13 - Reserved; TAP Timing

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 13 of 29 instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD ...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 14 of 29 2.5V TAP AC Test Conditions Input pulse levels .................................................V SS to 2.5V Input rise and fall time..................................................... 1 nsInput timing ...

Page 16 - 65-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 16 of 29 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9...

Page 17 - Electrical Characteristics

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 17 of 29 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.Storage Temperature ................................. –65 ° C to +150 ° C Ambient Te...

Page 19 - Switching Characteristics

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 19 of 29 Switching Characteristics Over the Operating Range [19, 20] Parameter Description 250 MHz 200 MHz 167 MHz Unit Min. Max Min. Max. Min. Max t POWER V DD (Typical) to the First Access [21] 1 1 1 ms Clock t ...

Page 20 - Switching Waveforms; Read Cycle Timing

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 20 of 29 Switching Waveforms Read Cycle Timing [25] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW, BWE, BWx Data Out (Q) High-Z t CLZ tDOH tCO ADV t OEHZ t CO Single READ BURST RE...

Page 21 - Write Cycle Timing

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 21 of 29 Write Cycle Timing [25, 26] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X Data Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1...

Page 22 - Read/Write Cycle Timing

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 22 of 29 Read/Write Cycle Timing [25, 27, 28] Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE, BW X Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D...

Page 23 - ZZ Mode Timing

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 23 of 29 ZZ Mode Timing [29, 30] Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 29. Device must b...

Page 24 - Ordering Information; for actual products offered.

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 24 of 29 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) O...

Page 26 - Package Diagrams

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-085050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUS...

Page 29 - Document History Page; SRAM

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25 Document #: 38-05546 Rev. *E Page 29 of 29 Document History Page Document Title: CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/CY7C1382FV25, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05546 REV. ECN NO. Issue Date Orig. of Change Desc...