Cypress CY7C1372DV25 - Manuals

Cypress CY7C1372DV25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1372DV25

Summary

Page 2 - Selection Guide; Unit

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 2 of 27 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGIS...

Page 3 - Pin Configurations

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A...

Page 5 - TMS

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 5 of 27 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE...

Page 6 - Pin Definitions

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 6 of 27 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d Input- Synchronous Byte Write Select I...

Page 7 - Introduction

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 7 of 27 Introduction Functional Overview The CY7C1370DV25 and CY7C1372DV25 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through input regi...

Page 8 - DD; ZZ Mode Electrical Characteristics

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 8 of 27 signals. The CY7C1370DV25/CY7C1372DV25 provides bytewrite capability that is described in the Write Cycle Descriptiontable. Asserting the Write Enable input (WE) with the selectedByte Write Select (BW) input will selectively write to...

Page 10 - Disabling the JTAG Feature; TAP Controller State Diagram; Performing a TAP Reset; WE

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 10 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370DV25/CY7C1372DV25 incorporates a serialboundary scan test access port (TAP).This part is fullycompliant with 1149.1. The TAP operates usingJEDEC-standard 3.3V or 2.5V I/O logic lev...

Page 11 - TAP Registers; ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 11 of 27 TAP Registers Registers are connected between the TDI and TDO balls andallow data to be scanned into and out of the SRAM testcircuitry. Only one register can be selected at a time throughthe instruction register. Data is serially lo...

Page 12 - TAP Timing; Test Clock

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 12 of 27 BYPASS When the BYPASS instruction is loaded in the instructionregister and the TAP is placed in a Shift-DR state, the bypassregister is placed between the TDI and TDO balls. Theadvantage of the BYPASS instruction is that it shorten...

Page 13 - TAP AC Switching Characteristics

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 13 of 27 TAP AC Switching Characteristics Over the Operating Range [9, 10] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 14 of 27 2.5V TAP AC Test Conditions Input pulse levels ................................................ V SS to 2.5V Input rise and fall time ..................................................... 1 ns Input timing reference levels ............

Page 16 - 65-Ball FBGA Boundary Scan Order; Ball ID; Internal

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 16 of 27 165-Ball FBGA Boundary Scan Order [12, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P...

Page 17 - Electrical Characteristics

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ..............................

Page 18 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 18 of 27 Capacitance [17] Parameter Description Test Conditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 2.5V. V DDQ = 2.5V 5 8 9 pF C CLK Clock Input Capacitance 5 8 9 pF ...

Page 19 - Switching Characteristics

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 19 of 27 Switching Characteristics Over the Operating Range [22, 23] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle Time ...

Page 20 - Switching Waveforms

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 20 of 27 Switching Waveforms Read/Write/Timing [24, 25, 26] Notes: 24. For this waveform ZZ is tied LOW.25. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 26. Order of...

Page 22 - Ordering Information; Commercial

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 22 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram ...

Page 23 - visit

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 23 of 27 250 CY7C1370DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1372DV25-250AXC CY7C1370DV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGC CY7C1370DV25-250BG...

Page 24 - Package Diagrams

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIME...

Page 27 - Document History Page; Issue Date

CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 27 of 27 Document History Page Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18)Pipelined SRAM with NoBL™ Architecture Document Number: 38-05558 REV. ECN No. Issue Date Orig. of Change Description of Change ** 254509 See ...