Cypress CY7C1354CV25 - Manuals

Cypress CY7C1354CV25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1354CV25

Summary

Page 2 - Selection Guide; Unit

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGIS...

Page 3 - Pin Configurations

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A...

Page 5 - TMS

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 5 of 28 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V...

Page 6 - Pin Definitions

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 6 of 28 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a, BW b, BW c, BW d, Input- Synchronous Byte Write Sele...

Page 7 - Functional Overview

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 7 of 28 Functional Overview The CY7C1354CV25 and CY7C1356CV25 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through input registers control...

Page 8 - ZZ Mode Electrical Characteristics

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 8 of 28 order to greatly simplify Read/Modify/Write sequences, whichcan be reduced to simple Byte Write operations. Because the CY7C1354CV25 and CY7C1356CV25 arecommon I/O devices, data should not be driven into the devicewhile the outputs a...

Page 10 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; The ball is pulled up internally, resulting in a logic HIGH level.; TAP Controller Block Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 10 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354CV25/CY7C1356CV25 incorporates a serialboundary scan test access port (TAP) in the BGA packageonly. The TQFP package does not offer this functionality. Thispart operates in accorda...

Page 11 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 11 of 28 It is also loaded with the IDCODE instruction if the controller isplaced in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the twoleast significant bits are loaded with a bina...

Page 12 - Test Clock

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 12 of 28 TAP Timing TAP AC Switching Characteristics Over the Operating Range [11, 12] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH Time 20 ns t TL TCK Clock...

Page 13 - TDO

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 13 of 28 2.5V TAP AC Test Conditions Input pulse levels ............................................... V SS to 2.5V Input rise and fall time .................................................... 1 ns Input timing reference levels ..............

Page 16 - Electrical Characteristics

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 16 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ..............................

Page 17 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 17 of 28 Capacitance [16] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V, V DDQ = 2.5V 5 5 5 pF C CLK Clock Input Capacitance 5 5 5 pF C I/O Input...

Page 18 - Switching Characteristics

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 18 of 28 Switching Characteristics Over the Operating Range [18, 19] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle Time ...

Page 19 - Switching Waveforms

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 19 of 28 Switching Waveforms Read/Write Timing [23, 24, 25] Notes: 23. For this waveform ZZ is tied LOW.24. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 25. Order of ...

Page 20 - NOP, STALL and DESELECT CYCLES

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 20 of 28 NOP, STALL and DESELECT CYCLES [23, 24, 26] Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Switching Waveforms (continued) READ Q(A3...

Page 21 - ZZ Mode Timing

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 21 of 28 ZZ Mode Timing [27, 28] Notes: 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.28. I/Os are in High-Z when exiting ZZ sleep mode. Switching W...

Page 22 - Ordering Information; Commercial

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 22 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram ...

Page 23 - visit

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 23 of 28 200 CY7C1354CV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-200AXC CY7C1354CV25-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356CV25-200BGC CY7C1354CV25-200BG...

Page 25 - Package Diagrams

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIME...

Page 28 - Document History Page; Issue Date

CY7C1354CV25CY7C1356CV25 Document #: 38-05537 Rev. *H Page 28 of 28 Document History Page Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18)Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05537 REV. ECN No. Issue Date Orig. of Change Description of Change ** 242032 See ...