Cypress CY7C1346H - Manuals

Page 2 - Unit

CY7C1346H Document #: 38-05672 Rev. *B Page 2 of 16 Pin Configuration Selection Guide 166 MHz Unit Maximum Access Time 3.5 ns Maximum Operating Current 240 mA Maximum CMOS Standby Current 40 mA A A A A A 1 A 0 N C /72M N C /36M V SS V DD NC/1 8 M NC/9M A A A A A A NC/ 4M DQP B DQ B DQ B V DDQ V SSQ ...

Page 3 - Pin Definitions

CY7C1346H Document #: 38-05672 Rev. *B Page 3 of 16 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled activ...

Page 4 - Functional Overview

CY7C1346H Document #: 38-05672 Rev. *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. The CY7C1346H supports secondary cache in s...

Page 5 - Burst Sequences; ZZ Mode Electrical Characteristics

CY7C1346H Document #: 38-05672 Rev. *B Page 5 of 16 Burst Sequences The CY7C1346H provides a two-bit wraparound counter, fedby A 1 , A 0 , that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specif-ically to support Intel Pentium applications. T...

Page 6 - Truth Table

CY7C1346H Document #: 38-05672 Rev. *B Page 6 of 16 Truth Table [2, 3, 4, 5, 6, 7] Next Cycle Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State Deselect Cycle, Powe...

Page 8 - Electrical Characteristics

CY7C1346H Document #: 38-05672 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied ..........................................

Page 9 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1346H Document #: 38-05672 Rev. *B Page 9 of 16 Capacitance [10] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V. V DDQ = 2.5V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resistance [10] ...

Page 10 - Switching Characteristics

CY7C1346H Document #: 38-05672 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [11, 12] Parameter Description -166 Unit Min. Max. t POWER V DD (Typical) to the First Access [13] 1 ms Clock t CYC Clock Cycle Time 6.0 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output Time...

Page 11 - Switching Waveforms; Read Cycle Timing

CY7C1346H Document #: 38-05672 Rev. *B Page 11 of 16 Switching Waveforms Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t...

Page 12 - Write Cycle Timing

CY7C1346H Document #: 38-05672 Rev. *B Page 12 of 16 Write Cycle Timing [17, 18] Note: 18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW[A :D...

Page 13 - Read/Write Cycle Timing

CY7C1346H Document #: 38-05672 Rev. *B Page 13 of 16 Read/Write Cycle Timing [17, 19, 20] Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.20. GW is HIGH. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE A...

Page 14 - ZZ Mode Timing; CLK

CY7C1346H Document #: 38-05672 Rev. *B Page 14 of 16 ZZ Mode Timing [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.22. DQs are in High-Z when exiting ZZ sleep mode. Switching Waveforms (conti...

Page 15 - Ordering Information; Commercial; Package Diagrams

CY7C1346H Document #: 38-05672 Rev. *B Page 15 of 16 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

Page 16 - Document History Page; Issue Date

CY7C1346H Document #: 38-05672 Rev. *B Page 16 of 16 Document History Page Document Title: CY7C1346H 2-Mbit (64K x 36) Pipelined Sync SRAMDocument Number: 38-05672 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347357 See ECN PCI New Data sheet *A 420879 See ECN RXU Converted from ...