Cypress CY7C1336H - Manuals

Page 2 - PRELIMINARY; Selection Guide; Unit; Pin Configuration; CE

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 2 of 15 Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum Standby Current 40 40 mA Pin Configuration 100-pin TQFP Pinout A A A A A 1 A 0 N C /72M N C /36M V SS V DD NC/9M A A A A A...

Page 3 - Pin Definitions

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 3 of 15 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are samp...

Page 4 - Functional Overview

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1336H supports secondary cache in s...

Page 5 - ZZ Mode Electrical Characteristics

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 5 of 15 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ ...

Page 6 - Truth Table for Read/Write; Read

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 6 of 15 Truth Table for Read/Write [2, 3] Function GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte (A, DQP A ) H L H H H L Write Byte (B, DQP B ) H L H H L H Write Bytes (B, A, DQP A , DQP B ) H L H H L L Write Byte (C,...

Page 7 - Maximum Ratings; Electrical Characteristics

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied .............................

Page 8 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 8 of 15 Capacitance [9] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V, V DDQ = 3.3V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resi...

Page 9 - Switching Characteristics

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 9 of 15 Switching Characteristics Over the Operating Range [10, 11] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (Typical) to the First Access [12] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 2....

Page 10 - Timing Diagrams; Read Cycle Timing

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 10 of 15 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1...

Page 11 - Write Cycle Timing

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 11 of 15 Write Cycle Timing [16, 17] Note: 17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ...

Page 13 - ZZ Mode Timing; CLK

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 13 of 15 ZZ Mode Timing [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.21. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagra...

Page 14 - Ordering Information; Commercial; Package Diagram

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in ...

Page 15 - Document History Page; Issue Date

PRELIMINARY CY7C1336H Document #: 001-00210 Rev. *A Page 15 of 15 Document History Page Document Title: CY7C1336H 2-Mbit (64K x 32) Flow-Through Sync SRAMDocument Number: 001-00210 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NX...