Cypress CY7C1320JV18 - Manuals

Cypress CY7C1320JV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1320JV18

Summary

Page 2 - Array

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 2 of 26 Logic Block Diagram (CY7C1316JV18) Logic Block Diagram (CY7C1916JV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W DQ [7:0] Output Logic...

Page 3 - rray

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 3 of 26 Logic Block Diagram (CY7C1318JV18) Logic Block Diagram (CY7C1320JV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W DQ [17:0] Output Logi...

Page 4 - Pin Configuration

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 4 of 26 Pin Configuration The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1316JV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M ...

Page 6 - Pin Definitions; Application Example

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 6 of 26 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Sampled on the rising edge of K and K clocks during valid write operations. These pins drive ...

Page 8 - Functional Overview; Write Operations

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 8 of 26 Functional Overview The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, andCY7C1320JV18 are synchronous pipelined Burst SRAMsequipped with a DDR interface, which operates with a readlatency of one and half...

Page 9 - with V; Echo Clocks; Switching; DLL; DLL Considerations; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 9 of 26 driver impedance. The value of RQ must be 5x the value of theintended line impedance driven by the SRAM. The allowablerange of RQ to guarantee impedance matching with a toleranceof ±15% is between 17...

Page 10 - Write Cycle Descriptions

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 10 of 26 Truth Table The truth table for the CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle:Load address; wait one cycle; input wr...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 12 of 26 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 13 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thed...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 14 of 26 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0...

Page 16 - Figure 2

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 16 of 26 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 18 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R...

Page 19 - Power Up Sequence in DDR-II SRAM; Power Up Sequence; Power Up Waveforms

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 19 of 26 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Duringpower up, when the DOFF is tied HIGH, the DLL is locked ...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 20 of 26 Maximum Ratings Exceeding maximum ratings may shorten the battery life of thedevice. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Tem...

Page 21 - Capacitance; Thermal Resistance

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 21 of 26 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V...

Page 22 - Switching Characteristics

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 22 of 26 Switching Characteristics Over the Operating Range [19] Cypress Parameter Consortium Parameter Description 300 MHz Unit Min Max t POWER V DD (Typical) to the first Access [20] 1 – ms t CYC t KHKH K ...

Page 23 - Switching Waveforms; LD; CQD

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 23 of 26 Switching Waveforms Figure 3. Read/Write/Deselect Sequence [24, 25, 26] READ READ READ NOP NOP WRITE WRITE NOP 1 2 3 4 5 6 7 8 9 10 Q40 t KHCH tCO t tHC t tHA tSD tHD t KHCH tSD tHD DON’T CARE UNDEF...

Page 24 - Ordering Information; for actual products offered.

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 24 of 26 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (M...

Page 25 - Package Diagram

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 Document Number: 001-15271 Rev. *B Page 25 of 26 Package Diagram Figure 4. 165-ball FBGA (13 x 15 x 1.40 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±...

Page 26 - Document History Page; ISSUE; See ECN VKN/KKVTMP New data sheet; specs; See ECN

Document Number: 001-15271 Rev. *B Revised March 10, 2008 Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...