Cypress CY7C1320CV18-250BZC - Manuals

Cypress CY7C1320CV18-250BZC – Manual in PDF format online.

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Manual

Manual Cypress CY7C1320CV18-250BZC

Summary

Page 2 - rray; Array

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 2 of 26 Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 36 18 BWS [1:0] V ...

Page 3 - Pin Configuration

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 3 of 26 Pin Configuration The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1318CV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS 1 K NC/144M LD A NC/36M CQ B NC ...

Page 4 - Pin Definitions; Application Example

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 4 of 26 Pin Definitions Pin Name I/O Pin Description DQ [x:0] Input Output- Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the request...

Page 6 - Functional Overview; Write Operations

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 6 of 26 Functional Overview The CY7C1318CV18, and CY7C1320CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is ...

Page 7 - Programmable Impedance; Echo Clocks; Switching; DLL; DLL Considerations in QDRIITM/DDRII; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 7 of 26 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impe...

Page 8 - Write Cycle Descriptions

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 8 of 26 Truth Table The truth table for the CY7C1318CV18, and CY7C1320CV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(...

Page 9 - BWS

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 9 of 26 Write Cycle Descriptions The write cycle description table for CY7C1320CV18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D [35:0] ) are written ...

Page 10 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 10 of 26 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC stan...

Page 12 - TAP Controller State Diagram; The state diagram for the TAP controller follows.

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 12 of 26 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 ...

Page 14 - Figure 2

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 14 of 26 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup T...

Page 16 - Boundary Scan Order; Bump ID; Internal

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 16 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 ...

Page 17 - Power Up Sequence in DDR II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 17 of 26 Power Up Sequence in DDR II SRAM DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can b...

Page 18 - Neutron Soft Error Immunity; DC Electrical Characteristics

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 18 of 26 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Appli...

Page 19 - AC Electrical Characteristics; Capacitance; ZQ

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 19 of 26 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 267 MHz (x18) 315 mA (x36) 330 250 MHz (x18) 300 (x36) 320 200 MHz (x18) 290 (x36) 300 167 MHz...

Page 20 - Switching Characteristics

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 20 of 26 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 267 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (Typical) to the First Access [22...

Page 22 - Switching Waveforms; LD; CQD

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 22 of 26 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ READ READ NOP NOP WRITE WRITE NOP 1 2 3 4 5 6 7 8 9 10 Q40 t KHCH tCO t tHC t tHA tSD tHD t KHCH tSD tHD DON’T CARE UNDEFINED tCLZ tDOH tCHZ SC tKH t...

Page 23 - Ordering Information

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 23 of 26 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress webs...

Page 24 - Package Diagram

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 24 of 26 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 51-85180-*B A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.08 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 ...

Page 25 - Document History Page; Date

CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 25 of 26 Document History Page Document Title: CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-07160 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 433284 See ECN NXR...

Page 26 - Worldwide Sales and Design Support; closest to you, visit us at; Products; PSoC

Document Number: 001-07160 Rev. *F Revised August 24, 2009 Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY...