Cypress CY7C1320BV18 - Manuals

Cypress CY7C1320BV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1320BV18

Summary

Page 2 - rray

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 2 of 31 Logic Block Diagram (CY7C1316BV18) Logic Block Diagram (CY7C1916BV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg....

Page 3 - Array

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 3 of 31 Logic Block Diagram (CY7C1318BV18) Logic Block Diagram (CY7C1320BV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg....

Page 4 - Pin Configuration

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1316BV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11...

Page 6 - Pin Definitions; Application Example

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 6 of 31 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These p...

Page 8 - Functional Overview; Write Operations

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 8 of 31 Functional Overview The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, andCY7C1320BV18 are synchronous pipelined Burst SRAMsequipped with a DDR interface. Accesses are initiated on the rising edge of the p...

Page 9 - Programmable Impedance; to enable the SRAM to adjust its output; Echo Clocks; Switching; DLL; AN5062, DLL Considerations in; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 9 of 31 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pinon the SRAM and V SS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value...

Page 10 - Write Cycle Descriptions

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 10 of 31 Truth Table The truth table for the CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle:Load address; wait one cycle; input wri...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 12 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-1900. The TAP ...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 13 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thede...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 14 of 31 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 ...

Page 16 - Figure 2

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 16 of 31 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL ...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 18 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R...

Page 19 - Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 19 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or L...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 20 of 31 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient ...

Page 21 - AC Electrical Characteristics

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 21 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 580 (x18) 600 (x36) 635 167 MHz (x8) 490 mA (x9) 490 (x18) 510 (x36) 540 I SB1 Automatic Power D...

Page 22 - Capacitance; Thermal Resistance

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 22 of 31 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V ...

Page 23 - Switching Characteristics

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 23 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t P...

Page 25 - Switching Waveforms; LD; CQD

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 25 of 31 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ READ READ NOP NOP WRITE WRITE NOP 1 2 3 4 5 6 7 8 9 10 Q40 t KHCH tCO t tHC t tHA tSD tHD t KHCH tSD tHD DON’T CARE UNDEFI...

Page 26 - Ordering Information; for actual products offered.

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 26 of 31 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (M...

Page 29 - Package Diagram

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 29 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0....

Page 30 - Document History Page; Submission

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 30 of 31 Document History Page Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Ar-chitectureDocument Number: 38-05621 Rev. ECN No. Submission Date Orig, o...