Cypress CY7C1319CV18 - Manuals

Cypress CY7C1319CV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1319CV18

Summary

Page 4 - Pin Configuration

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1317CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 1...

Page 6 - Pin Definitions; Application Example

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 6 of 31 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These ...

Page 8 - Functional Overview; Read Operations; Write Operations; Single Clock Mode

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 8 of 31 Functional Overview The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, andCY7C1321CV18 are synchronous pipelined Burst SRAMsequipped with a DDR interface, which operates with a readlatency of one and half...

Page 9 - to enable the SRAM to adjust its output; Echo Clocks; Switching; DLL; DLL Considerations in QDRIITM/DDRII

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 9 of 31 after the read(s), the stored data from the earlier write is writteninto the SRAM array. This is called a posted write. If a read is performed on the same address on which a write isperformed in the ...

Page 10 - Figure 1; Truth Table; ohms; BUS

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 10 of 31 Application Example Figure 1 shows two DDR-II used in an application. Figure 1. Application Example Truth Table The truth table for the CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 fol...

Page 11 - Burst Address Table

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 11 of 31 Burst Address Table (CY7C1319CV18, CY7C1321CV18) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X..X00 X..X01 X..X10 X..X11 X..X01 X..X10 X..X1...

Page 12 - BWS

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 12 of 31 Write Cycle Descriptions The write cycle description table for CY7C1321CV18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the data portion of a write sequence, all four b...

Page 13 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 13 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP...

Page 14 - and t; ). The SRAM clock input might not be captured

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 14 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thed...

Page 15 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 15 of 31 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0...

Page 17 - Figure 2

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 17 of 31 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 19 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R...

Page 20 - Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 20 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or ...

Page 21 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 21 of 31 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient...

Page 22 - AC Electrical Characteristics

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 22 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 580 mA (x9) 580 (x18) 600 (x36) 655 167 MHz (x8) 515 mA (x9) 515 (x18) 540 (x36) 600 I SB1 Automatic Power ...

Page 23 - Capacitance; Thermal Resistance

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 23 of 31 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V...

Page 24 - Switching Characteristics

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 24 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t ...

Page 26 - Switching Waveforms; DON’T CARE

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 26 of 31 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [27, 28, 29] K 1 2 3 4 5 6 7 8 9 10 11 12 13 A DQ C READ(burst of 4) READ(burst of 4) READ(burst of 4) NOP NOP WRITE(burst of 4) WRITE(burs...

Page 27 - Ordering Information; for actual products offered.

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 27 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (M...

Page 30 - Package Diagram

CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 30 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0...

Page 31 - Document History Page; Submission

Document Number: 001-07161 Rev. *D Revised June 18, 2008 Page 31 of 31 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7C...