Cypress CY7C1310BV18 - Manuals

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Manual Cypress CY7C1310BV18

Summary

Page 2 - DOFF; DOFF

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 2 of 29 Logic Block Diagram (CY7C1310BV18) Logic Block Diagram (CY7C1910BV18) 1M x 8 A rray CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic Addre...

Page 3 - Array

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) 512 K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic A...

Page 4 - Pin Configuration

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 4 of 29 Pin Configuration The pin configuration for CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1310BV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ...

Page 6 - Pin Definitions; Application Example

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1310BV18 - D [7:0] CY7C1910BV18 - ...

Page 8 - Functional Overview; Write Operations

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 8 of 29 Functional Overview The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, andCY7C1314BV18 are synchronous pipelined Burst SRAMsequipped with a read port and a write port. The read port isdedicated to read operatio...

Page 9 - Programmable Impedance; to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; AN5062, DLL Considerations in; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 9 of 29 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pinon the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 12 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-1900. The TAP opera...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevice ...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 14 of 29 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 0 1...

Page 16 - Figure 2

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 16 of 29 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK C...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9...

Page 19 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (a...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 20 of 29 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Tempe...

Page 21 - AC Electrical Characteristics

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 21 of 29 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 250 MHz (x8) 400 mA (x9) 400 (x18) 400 (x36) 450 200 MHz (x8) 380 mA (x9...

Page 22 - Capacitance; Thermal Resistance

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 22 of 29 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = ...

Page 24 - Switching Waveforms; RPS

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 24 of 29 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] K 1 2 3 4 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 tKH tKHKH tKL tCYC t tHC tSA tHA tSD tHD SC t...

Page 25 - Ordering Information; for actual products offered.

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 25 of 29 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) O...

Page 27 - Package Diagram

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0....

Page 28 - Document History Page; Submission

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 28 of 29 Document History Page Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR™-II SRAM 2-Word Burst ArchitectureDocument Number: 38-05619 Rev. ECN No. Submission Date Orig, of Cha...