Cypress CY7C1310AV18 - Manuals

Cypress CY7C1310AV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1310AV18

Summary

Page 2 - PRELIMINARY; Selection Guide; Unit; ra; Arr

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 2 of 21 Selection Guide 167 MHz 133 MHz Unit Maximum Operating Frequency 167 133 MHz Maximum Operating Current 800 700 mA Logic Block Diagram (CY7C1312AV18) CLK A (18:0) Gen. K K Control Logic Address Register D [17...

Page 3 - Pin Configurations

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 3 of 21 Pin Configurations CY7C1310AV18 (2M × 8) – 11 × 15 BGA 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R A CQ NCNCNC NC DOFF NC V SS /72M A BWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5 NC NC NC TCK NC NC A NC/288M...

Page 4 - Pin Definitions; Pin Name

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 4 of 21 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1310AV18 - D [7:0] CY7C1312AV18 - ...

Page 6 - Introduction

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 6 of 21 Introduction Functional Overview The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operation...

Page 7 - Application Example

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 7 of 21 Depth Expansion The CY7C1312AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port ...

Page 8 - Write Cycle Descriptions

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 8 of 21 Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18) [2, 8] BWS 0 BWS 1 K K Comments L L L-H – During the Data portion of a Write sequence : CY7C1310AV18 − both nibbles (D [7:0] ) are written into the de...

Page 9 - Maximum Ratings; DC Electrical Characteristics

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 9 of 21 Maximum Ratings (Above which useful life may be impaired.)Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied ............................................

Page 10 - Switching Characteristics

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 10 of 21 Switching Characteristics Over the Operating Range [16,17] Cypress Consortium Description 167 MHz 133 MHz Unit Parameter Parameter Min. Max. Min. Max. t CYC t KHKH K Clock and C Clock Cycle Time 6.0 7.9 7.5...

Page 11 - Capacitance; Parameter; AC Test Loads and Waveforms

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 11 of 21 Capacitance [20] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5 pF C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF ...

Page 12 - Switching Waveforms

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 12 of 21 Switching Waveforms [21,22,23] Notes: 21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.22. Output are disabled (High-Z) one clock c...

Page 14 - SAMPLE Z; BYPASS

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 14 of 21 is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected be...

Page 15 - TAP Controller State Diagram

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 15 of 21 Note: 24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TAP Controller State Diagram [24] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE...

Page 16 - TAP Controller Block Diagram; TAP Controller

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 16 of 21 TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range [9,12,25] Parameter Description Test Conditions Min. Max. Unit V OH1 Output HIGH Voltage I OH = − 2.0 mA 1.4 V V OH2 Outp...

Page 17 - TAP AC Switching Characteristics; TAP Timing and Test Conditions

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 17 of 21 TAP AC Switching Characteristics Over the Operating Range [26, 27] Parameter Description Min. Max. Unit t TCYC TCK Clock Cycle Time 100 ns t TF TCK Clock Frequency 10 MHz t TH TCK Clock HIGH 40 ns t TL TCK ...

Page 18 - Identification Register Definitions

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 18 of 21 Identification Register Definitions Instruction Field CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Description 2M x 8 1M x 18 512K x 36 Revision Number (31:29) 000 000 000 Version number. Cypress Device ID (28:12...

Page 19 - Internal; Bump ID; Bump ID

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 19 of 21 30 11F 31 11G 32 9F 33 10F 34 11E 35 10E 36 10D 37 9E 38 10C 39 11D 40 9C 41 9D 42 11B 43 11C 44 9B 45 10B 46 11A 47 Internal 48 9A 49 8B 50 7C 51 6C 52 8A 53 7A 54 7B 55 6B 56 6A 57 5B 58 5A 59 4A 60 5C 61...

Page 20 - QDR; Ordering Information; Commercial; Package Diagram

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 20 of 21 QDR  SRAMs and Quad Data Rate  SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and Samsung technology. All product and company names mentioned in this document are the trad...

Page 21 - Document History Page; Change

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 21 of 21 Document History Page Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05497 REV. ECN No. Issue Date Orig. of Change Description of Cha...