Cypress CY7C1306BV25 - Manuals

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 5 of 19 Introduction Functional Overview The CY7C1303BV25/CY7C1306BV25 are synchronouspipelined Burst SRAM equipped with both a Read port and aWrite port. The Read port is dedicated to Read operations andthe Write port is dedicated to Write...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 6 of 19 operation is identical to the operation if the device had zeroskew between the K/K and C/C clocks. All timing parametersremain the same in this mode. To use this mode of operation,the user must tie C and C HIGH at power-up.This func...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 8 of 19 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliantwith IEEE Standard #1149.1-1900. The TAP operates usingJEDEC standard 2.5V...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 9 of 19 is loaded into the instruction register upon power-up orwhenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan registerto be connected between the TDI and TDO pins w...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 10 of 19 TAP Controller State Diagram [9] Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELE...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 12 of 19 Output Times t TDOV TCK Clock LOW to TDO Valid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions [12] TAP AC Switching Characteristics Over the Operating Range [11, 12] (continued) Parameter Description ...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 13 of 19 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the ...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 14 of 19 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 6...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 15 of 19 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature withPower Applied ............................................ –55°C to + 125°...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 17 of 19 Switching Waveforms [25, 26, 27] Notes: 24. t CHZ , t CLZ , are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 25. Q00 refers to output from add...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 18 of 19 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied ...

CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev. *A Page 19 of 19 Document History Page Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ ArchitectureDocument Number: 38-05627 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 253010 See ECN SYT N...