Cypress CY7C1243V18 - Manuals

Cypress CY7C1243V18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1243V18

Summary

Page 2 - rr; DOFF; DOFF

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 2 of 28 Logic Block Diagram (CY7C1241V18) Logic Block Diagram (CY7C1256V18) 1M x 8 A rr a y CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. D e cod e Read Data Reg. RPS WPS Q [7:0] Control...

Page 3 - rray

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 3 of 28 Logic Block Diagram (CY7C1243V18) Logic Block Diagram (CY7C1245V18) 512K x 18 Arra y CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Re ad Add. Decode Read Data Reg. RPS WPS Q [17:0] Contro...

Page 4 - Pin Configurations

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 4 of 28 Pin Configurations CY7C1241V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A BCD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5...

Page 6 - Pin Definitions

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks during valid write operations. CY7C1241V18 − D [7:0] CY7C1256V18 −...

Page 8 - Functional Overview; Read Operations; Write Operations; Concurrent Transactions

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 8 of 28 Functional Overview The CY7C1241V18, CY7C1256V18, CY7C1243V18, andCY7C1245V18 are synchronous pipelined Burst SRAMsequipped with a read and a write port. The read port is dedicatedto read operations and ...

Page 9 - to enable the SRAM to adjust its output; Echo Clocks; echo clocks is shown in

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 9 of 28 Depth Expansion The CY7C1243V18 has a Port Select input for each port. Thisenables easy depth expansion. Both Port Selects are sampledon the rising edge of the Positive Input Clock only (K). Each portsel...

Page 10 - Application Example; Figure 1; Truth Table; Stopped X; DATA IN

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 10 of 28 Application Example Figure 1 shows the use of 4 QDR-II+ SRAMs in an application. Figure 1. Application Example Truth Table The truth table for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 ...

Page 12 - Write Cycle Descriptions; BWS

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 12 of 28 Write Cycle Descriptions The write cycle description table for CY7C1245V18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes...

Page 13 - Instruction Register; Boundary Scan Register

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 13 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP ope...

Page 14 - and t; ). The SRAM clock input might not be captured

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 14 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevic...

Page 15 - TAP Controller State Diagram

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 15 of 28 TAP Controller State Diagram The state diagram for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows. [11] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAU...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 19 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 ...

Page 20 - Figure 2. Power Up Waveforms; Unstable Clock

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 20 of 28 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Duringpower up, when the DOFF is tied HIGH, the DLL is locked af...

Page 21 - Electrical Characteristics; DC Electrical Characteristics

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 21 of 28 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperat...

Page 22 - Capacitance; Thermal Resistance

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 22 of 28 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD ...

Page 23 - Switching Characteristics

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 23 of 28 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consortium Parameter Description 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max t POWER V DD (Typical) to the First Ac...

Page 24 - Switching Waveforms; WPS

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 24 of 28 Switching Waveforms Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency [30, 31, 32] t KH t KL t CYC t KHKH NOP READ NOP WRITE READ WRITE 1 2 3 4 5 6 7 8 t t t tSA HA SC HC t HD t...

Page 25 - Ordering Information; for actual products offered.

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 25 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 27 - Package Diagram

CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 27 of 28 Package Diagram Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - ....

Page 28 - Document History Page; ISSUE

Document Number: 001-06365 Rev. *D Revised March 12, 2008 Page 28 of 28 QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. Allproduct and company names mentioned in this document ...