Cypress CY7C1231H - Manuals

Page 2 - Selection Guide; Unit; Pin Configuration

CY7C1231H Document #: 001-00207 Rev. *B Page 2 of 12 Selection Guide 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 225 mA Maximum CMOS Standby Current 40 mA Pin Configuration 100-pin TQFP Pinout A A A A A1 A0 NC/ 28 8M NC/144M V SS V DD NC(36M) A A A A A NC /4 M A NC NC V DDQ V S...

Page 3 - Pin Definitions

CY7C1231H Document #: 001-00207 Rev. *B Page 3 of 12 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 128K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW [A:B] Input- Synchronou...

Page 4 - Functional Overview; Single Read Accesses; Sleep Mode

CY7C1231H Document #: 001-00207 Rev. *B Page 4 of 12 Functional Overview The CY7C1231H is a synchronous flow-through burst SRAMdesigned specifically to eliminate wait states duringWrite-Read transitions. All synchronous inputs pass throughinput registers controlled by the rising edge of the clock. T...

Page 6 - Electrical Characteristics

CY7C1231H Document #: 001-00207 Rev. *B Page 6 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied .............................................

Page 7 - Capacitance; Input Capacitance; pF; Clock Input Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1231H Document #: 001-00207 Rev. *B Page 7 of 12 Capacitance [11] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 pF C CLOCK Clock Input Capacitance 5 pF C I/O I/O Capacitance 5 pF Thermal Resistance [11] Parameter...

Page 8 - Switching Characteristics

CY7C1231H Document #: 001-00207 Rev. *B Page 8 of 12 Switching Characteristics Over the Operating Range [12, 13] Parameter Description -133 Unit Min. Max. t POWER V DD (Typical) to the first Access [14] 1 ms Clock t CYC Clock Cycle Time 7.5 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output Time...

Page 9 - Switching Waveforms

CY7C1231H Document #: 001-00207 Rev. *B Page 9 of 12 Switching Waveforms Read/Write Waveforms [18, 19, 20] Notes: 18. For this waveform ZZ is tied LOW.19. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst s...

Page 11 - Ordering Information; Commercial; Package Diagram

CY7C1231H Document #: 001-00207 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pr...

Page 12 - Document History Page; Issue Date

CY7C1231H Document #: 001-00207 Rev. *B Page 12 of 12 Document History Page Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ ArchitectureDocument Number: 001-00207 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 Se...