Cypress CY7C1223H - Manuals

Page 2 - Logic Block Diagram

CY7C1223H Document #: 38-05674 Rev. *B Page 2 of 16 Logic Block Diagram ADDRESSREGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BW B BW A CE 1 DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP A BYTE WRITE REGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 A [1:0] MODE CE 2 CE 3 GW BWE PIPEL...

Page 3 - Pin Configurations; Top View

CY7C1223H Document #: 38-05674 Rev. *B Page 3 of 16 Pin Configurations 100-pin TQFP Pinout ANCNCV DDQ V SSQ NCDQP A DQ A DQ A V SSQ V DDQ DQ A DQ A V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A NCNCV SSQ V DDQ NCNCNC NCNCNC V DDQ V SSQ NCNC DQ B DQ B V SSQ V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DD...

Page 4 - Pin Descriptions

CY7C1223H Document #: 38-05674 Rev. *B Page 4 of 16 Pin Descriptions Pin Type Description A0, A 1 , A Input- Synchronous Address Inputs used to select one of the 128K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled activ...

Page 5 - Functional Overview; Single Read Accesses; Single Write Accesses Initiated by ADSP; Burst Sequences

CY7C1223H Document #: 38-05674 Rev. *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. The CY7C1223H supports secondary cache in s...

Page 6 - Truth Table

CY7C1223H Document #: 38-05674 Rev. *B Page 6 of 16 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A...

Page 8 - Electrical Characteristics

CY7C1223H Document #: 38-05674 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature .................................... –65°C to +150° Ambient Temperature withPower Applied ............................................

Page 9 - Capacitance; Thermal Characteristics; AC Test Loads and Waveforms

CY7C1223H Document #: 38-05674 Rev. *B Page 9 of 16 Capacitance [9] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Characteristics [9...

Page 10 - Switching Characteristics

CY7C1223H Document #: 38-05674 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [14, 15] Parameter Description 166 MHz 133 MHz Unit Min. Max. Min. Max. t POWER V DD (Typical) to the first Access [10] 1 1 ms Clock t CYC Clock Cycle Time 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t ...

Page 11 - Switching Waveforms; Read Timing

CY7C1223H Document #: 38-05674 Rev. *B Page 11 of 16 Switching Waveforms Read Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 ...

Page 12 - Write Timing

CY7C1223H Document #: 38-05674 Rev. *B Page 12 of 16 Write Timing [16, 17] Note: 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:B] LOW. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW [A:B] ADV ...

Page 14 - ZZ Mode Timing; CLK

CY7C1223H Document #: 38-05674 Rev. *B Page 14 of 16 ZZ Mode Timing [20,21] Notes: 20. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.21. DQs are in High-Z when exiting ZZ sleep mode. Switching Waveforms (continued) t ZZ I S...

Page 15 - Ordering Information; Commercial; Package Diagram

CY7C1223H Document #: 38-05674 Rev. *B Page 15 of 16 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

Page 16 - Document History Page; Issue Date

CY7C1223H Document #: 38-05674 Rev. *B Page 16 of 16 Document History Page Document Title: CY7C1223H 2-Mbit (128K x 18) Pipelined DCD Sync SRAMDocument Number: 38-05674 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN RXU Changed ad...