Cypress CY7C1161V18 - Manuals

Cypress CY7C1161V18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1161V18

Summary

Page 2 - K x 9 Array; DOFF

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 2 of 29 Logic Block Diagram (CY7C1161V18) Logic Block Diagram (CY7C1176V18) 512K x 8 Array CLK A (18:0) Gen. K K Control Logic Address Register D [7:0] Re ad Add. Decode Read Data Reg. RPS WPS Q [7:0] Control Lo...

Page 3 - Array

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 3 of 29 Logic Block Diagram (CY7C1163V18) Logic Block Diagram (CY7C1165V18) 256 K x 1 8 Array CLK A (17:0) Gen. K K Control Logic Address Register D [17:0] Read Add. De code Read Data Reg. RPS WPS Q [17:0] Contr...

Page 4 - Pin Configurations

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 4 of 29 Pin Configurations CY7C1161V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A BCD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5...

Page 6 - Pin Definitions; “Switching Characteristics”

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks during valid write operations. CY7C1161V18 − D [7:0] CY7C1176V18 −...

Page 8 - Functional Overview; Read Operations; Write Operations; Concurrent Transactions

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 8 of 29 Functional Overview The CY7C1161V18, CY7C1176V18, CY7C1163V18, andCY7C1165V18 are synchronous pipelined burst SRAMsequipped with both a read port and a write port. The read port isdedicated to read opera...

Page 9 - to enable the SRAM to adjust its output; Echo Clocks; the echo clocks are shown in the AC timing table.; DLL; .” The DLL can also be

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 9 of 29 Depth Expansion The CY7C1163V18 has a port select input for each port. Thisenables easy depth expansion. Both port selects are onlysampled on the rising edge of the positive input clock (K). Eachport sel...

Page 10 - Application Example; Figure 1; Truth Table; Stopped; DATA IN

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 10 of 29 Application Example Figure 1 shows four QDR-II+ used in an application. Figure 1. Application Example Truth Table The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows. ...

Page 11 - Write Cycle Descriptions

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 11 of 29 Write Cycle Descriptions The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow. [3, 11] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the data portion of a write sequence : CY7C...

Page 13 - Instruction Register; Boundary Scan Register

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 13 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliant withIEEE Standard 1149.1-2001. The TAP oper...

Page 14 - and t; ). The SRAM clock input is not captured correctly if there

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 14 of 29 IDCODE The IDCODE instruction causes a vendor-specific 32-bit code tobe loaded into the instruction register. It also places theinstruction register between the TDI and TDO pins and enablesthe IDCODE to...

Page 15 - TAP Controller State Diagram; Figure 2. Tap Controller State Diagram

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 15 of 29 TAP Controller State Diagram Figure 2. Tap Controller State Diagram [12] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELECTIR-SCAN CAPTURE-IR S...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 19 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32...

Page 20 - Figure 4. Power Up Waveforms; Unstable Clock

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 20 of 29 Power Up Sequence in QDR-II+ SRA During power up, when the DOFF is tied HIGH, the DLL getslocked after 2048 cycles of stable clock. QDR-II+ SRAMs mustbe powered up and initialized in a predefined manner...

Page 21 - Electrical Characteristics

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 21 of 29 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. User guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperatu...

Page 22 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 22 of 29 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD ...

Page 23 - Switching Characteristics

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 23 of 29 Switching Characteristics Over the operating range [23, 24] Cypress Parameter Consortium Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (Typical)...

Page 25 - Switching Waveforms; Figure 6. Waveform for 2.5 Cycle Read Latency

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 25 of 29 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5 Cycle Read Latency [31, 32, 33] t KH t KL t CYC t KHKH t t t tSA HA SC HC t HD tSC tHC A0 A1 A2 A3 t t SD HD t SD D11 D10 D12 ...

Page 26 - Ordering Information; for actual products offered.

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 26 of 29 Ordering Information Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Orderin...

Page 28 - Package Diagram

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18 Document Number: 001-06582 Rev. *D Page 28 of 29 Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 ...

Page 29 - Document History Page; Issue Date

Document Number: 001-06582 Rev. *D Revised March 06, 2008 Page 29 of 29 QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. Allproduct and company names mentioned in this document ...