Cypress CY7C1150V18 - Manuals

Cypress CY7C1150V18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1150V18

Summary

Page 2 - Array; Array

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1146V18) Logic Block Diagram (CY7C1157V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. D e code Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 ...

Page 3 - ray

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 3 of 27 Logic Block Diagram (CY7C1148V18) Logic Block Diagram (CY7C1150V18) CLK A (18:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic Reg. Reg. Reg. 18 18 3...

Page 4 - Pin Configurations

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 4 of 27 Pin Configurations CY7C1146V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K R/W NC/144M NC NC NC NC NC TDO NC NC N...

Page 6 - Pin Definitions; “Switching Characteristics”

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks when write operations are valid. These pi...

Page 8 - Functional Overview; Write Operations

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 8 of 27 Functional Overview The CY7C1146V18, CY7C1157V18, CY7C1148V18, andCY7C1150V18 are synchronous pipelined Burst SRAMsequipped with a DDR interface. Accesses are initiated on the rising edge of the positive...

Page 9 - DLL; Application Example; Figure 1; Figure 1. Application Example; Truth Table; Operation; BUS; DQ

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 9 of 27 echo clock and follows the timing of any data pin. This signal isasserted half a cycle before valid data arrives. DLL These chips utilize a Delay Lock Loop (DLL) that is designed tofunction between 120 M...

Page 10 - Write Cycle Descriptions

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 10 of 27 Write Cycle Descriptions The write cycle descriptions of CY7C1146V18 and CY7C1148V18 follows. [3, 9] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L – H – When the Data portion of a write sequence is act...

Page 12 - “TAP Controller State Diagram”; Instruction Register; Boundary Scan Register

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 12 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliant withIEEE Standard 1149.1-2001. The TAP oper...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 13 of 27 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded into the instruction register. It also places theinstruction register between the TDI and TDO pins and enablesthe IDCODE t...

Page 14 - TAP Controller State Diagram; Figure 2; Figure 2. Tap Controller State Diagram

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 14 of 27 TAP Controller State Diagram Figure 2 shows the tap controller state diagram. [10] Figure 2. Tap Controller State Diagram TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32...

Page 19 - Figure 5. Power Up Waveforms; Unstable Clock

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM During Power Up, when the DOFF is tied HIGH, the DLL getslocked after 2048 cycles of stable clock. DDR-II+ SRAMs mustbe powered up and initialized in a predefined manne...

Page 20 - Electrical Characteristics

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 20 of 27 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Te...

Page 21 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 21 of 27 Capacitance Tested initially and after any design or process change that may affect these parameters . Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD...

Page 22 - Switching Characteristics

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 22 of 27 Switching Characteristics Over the operating range [21, 22] Cypress Parameter Consortium Parameter Description 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max t POWER V DD (Typical) to the first Ac...

Page 23 - Switching Waveforms; Figure 7. Waveform for 2.0 Cycle Read Latency; DON’T CARE; t CQD

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence Figure 7. Waveform for 2.0 Cycle Read Latency [29, 30, 31] DON’T CARE UNDEFINED 1 2 3 4 5 6 7 8 9 10 READ READ READ NOP WRITE WRITE t NOP 11 K K LD R/W A...

Page 24 - Ordering Information; for actual products offered.

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 24 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Contact your local sales representative orvisit www.cypress.com for actual products offered. Speed (MHz) Ordering...

Page 26 - Package Diagram

CY7C1146V18, CY7C1157V18CY7C1148V18, CY7C1150V18 Document Number: 001-06621 Rev. *D Page 26 of 27 Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 ...

Page 27 - Document History Page; Issue Date

Document Number: 001-06621 Rev. *D Revised March 06, 2008 Page 27 of 27 QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. Allproduct and company names mentioned in this document ...