Cypress CY7C09179V - Manuals

Page 3 - Pin Configurations

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 3 of 21 Pin Configurations (continued Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 6...

Page 4 - Selection Guide; Description; Pin Definitions; Left Port

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 4 of 21 Notes 8. This pin is NC for CY7C09179V.9. This pin is NC for CY7C09179V and CY7C09189V Selection Guide Description CY7C09079V/89V/99V CY7C09179V/89V/99V-6 [1] CY7C09079V/89V/99V CY7C09179V/89V/99V-7 [1] CY7C09079V/89V/99...

Page 5 - Electrical Characteristics

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 5 of 21 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. [10] Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature...

Page 6 - including scope and jig); OUTPUT; ALL INPUT PULSES; cc

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 6 of 21 Figure 4. AC Test Loads (Applicable to -6 and -7 only) [13] Figure 5. Load Derating Curve Figure 3. AC Test Loads (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C = 30 pF V TH = 1.4V OUTPUT C = 30 pF (b) Thév...

Page 7 - Switching Characteristics

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 7 of 21 Notes 14. Test conditions used are Load 2.15. This parameter is guaranteed by design, but it is not production tested. Switching Characteristics Over the Operating Range Parameter Description CY7C09079V/89V/99V CY7C09179...

Page 8 - Switching Waveforms

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 8 of 21 Switching Waveforms (continued) Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = V IL ) [16, 17, 18, 19] Notes 16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.17. ADS...

Page 9 - Figure 8. Bank Select Pipelined Read

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 9 of 21 Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = V IH ) [16, 17, 18, 19] Figure 8. Bank Select Pipelined Read [20, 21] - Switching Waveforms (continued) t CH2 t CL2 t CYC2 t SC t HC t SW t HW t SA t HA A n A n+1 C...

Page 10 - Figure 9. Left Port Write to Flow-Through Right Port Read

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 10 of 21 Figure 9. Left Port Write to Flow-Through Right Port Read [22, 23, 24, 25] Notes 20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this...

Page 18 - Ordering Information

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 18 of 21 Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 [1] CY7C09079V-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 [1] CY7C09079V-7AC A1...

Page 20 - Package Diagram

CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev. *C Page 20 of 21 Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) 51-85048-*B [+] Feedback

Page 21 - Document History Page; Worldwide Sales and Design Support; RAM

Document #: 38-06043 Rev. *C Revised December 10, 2008 Page 21 of 21 All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C09079V/89V/99V CY7C09179V/89V/99V © Cypress Semiconductor Corporation, 2005-2008. The information contained herein is ...