Cypress CY7C0850AV - Manuals

Cypress CY7C0850AV – Manual in PDF format online.

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Manual

Manual Cypress CY7C0850AV

Summary

Page 2 - Logic Block Diagram; True

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 2 of 32 Logic Block Diagram [1] A 0L –A 17L CLK L ADS L CNTEN L CNTRST L True RAM Array 18 Addr. Read Back CNTINT L Mask Register Counter/ Address Register CNT/MSK L Address Decode Dual-Ported Interrupt Logic INT L Reset...

Page 3 - Pin Configurations

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 3 of 32 Pin Configurations Figure 1. 172-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9...

Page 6 - Pin Definitions

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 6 of 32 Pin Definitions Left Port Right Port Description A 0L –A 17L [1] A 0R –A 17R [1] Address Inputs . ADS L [3] ADS R [3] Address Strobe Input . Used as an address qualifier. This signal should be asserted LOW for th...

Page 7 - Table 2

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 7 of 32 Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- nously to the clocks. The MRST initializes the internal burst counters to zero, an...

Page 8 - counter register; Table 3; Counter Reset Operation; Figure 4; Counter Increment Operation; Figure 5; Counter Hold Operation

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 8 of 32 Address Counter and Mask Register Operations This section [10] describes the features only apply to CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to the CY7C0853AV device. Each port of these devices has a pro...

Page 11 - Figure 5. Programmable Counter-Mask Register Operation

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 11 of 32 Figure 5. Programmable Counter-Mask Register Operation [1, 12] 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 ...

Page 12 - Performing a TAP Reset

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 12 of 32 IEEE 1149.1 Serial Boundary Scan (JTAG) [13] The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that...

Page 13 - Electrical Characteristics

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 13 of 32 Maximum Ratings Exceeding maximum ratings [15] may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................ –65 ° C to + 150 ° C Ambient Tem...

Page 14 - Switching Characteristics; ALL INPUT PULSES; OUTPUT

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 14 of 32 Figure 6. AC Test Load and Waveforms Switching Characteristics Over the Operating Range Parameter Description -167 -133 -100 Unit CY7C0850AV CY7C0851AV CY7C0852AV CY7C0850AV CY7C0851AV CY7C0852AV CY7C0853AV CY7C...

Page 16 - JTAG Timing

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 16 of 32 JTAG Timing Parameter Description 167/133/100 Unit Min Max f JTAG Maximum JTAG TAP Controller Frequency 10 MHz t TCYC TCK Clock Cycle Time 100 ns t TH TCK Clock HIGH Time 40 ns t TL TCK Clock LOW Time 40 ns t TM...

Page 17 - Switching Waveforms; Figure 8. Master Reset

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 17 of 32 Switching Waveforms Figure 8. Master Reset Figure 9. Read Cycle [4, 22, 23, 24, 25] MRST t RSR t RS INACTIVE ACTIVE TMS TDO INT CNTINT t RSF t RSS ALL ADDRESS/ DATA LINES ALL OTHER INPUTS t CH2 t CL2 t CYC2 t SC...

Page 18 - Figure 10. Bank Select Read

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 18 of 32 Figure 10. Bank Select Read [26, 27] Figure 11. Read-to-Write-to-Read (OE = LOW) [25, 28, 29, 30, 31] Switching Waveforms (continued) Q 3 Q 1 Q 0 Q 2 A 0 A 1 A 2 A 3 A 4 A 5 Q 4 A 0 A 1 A 2 A 3 A 4 A 5 t SA t HA...

Page 19 - Figure 13. Read with Address Counter Advance

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 19 of 32 Figure 12. Read-to-Write-to-Read (OE Controlled) [25, 28, 30, 31] Figure 13. Read with Address Counter Advance [30] Switching Waveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA A n A n+1 A n+...

Page 20 - Figure 14. Write with Address Counter Advance

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 20 of 32 Figure 14. Write with Address Counter Advance [31] Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write Switching Waveforms (continued) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+...

Page 23 - Figure 19. Counter Reset

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 23 of 32 Figure 19. Counter Reset [32, 33] Switching Waveforms (continued) CLK ADDRESS INTERNAL CNTEN ADS DATA IN ADDRESS CNTRST R/W DATA OUT A n A m A p A x 0 1 A n A m A p Q 1 Q n Q 0 D 0 t CH2 t CL2 t CYC2 t SA t HA t...

Page 24 - Figure 20. Readback State of Address Counter or Mask Register

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 24 of 32 Figure 20. Readback State of Address Counter or Mask Register [35, 36, 37, 38] Switching Waveforms (continued) CNTEN CLK t CH2 t CL2 t CYC2 ADDRESS ADS A n Q x-2 Q x-1 Q n t SA t HA t SAD t HAD t SCN t HCN LOAD ...

Page 26 - Figure 22. Counter Interrupt and Retransmit

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 26 of 32 Figure 22. Counter Interrupt and Retransmit [34, 42, 43, 44, 45] Switching Waveforms (continued) t CH2 t CL2 t CYC2 CLK 1FFFD 1FFFF INTERNAL ADDRESS Last_Loaded Last_Loaded +1 t HCM COUNTER 1FFFE CNTINT t SCINT ...

Page 27 - Write; Read; CLK

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 27 of 32 Figure 23. MailBox Interrupt Timing [46, 47, 48, 49, 50] Table 7. Read/Write and Enable Operation (Any Port) [1, 8, 51, 52] Inputs Outputs Operation OE CLK CE 0 CE 1 R/W DQ 0 – DQ 35 X H X X High-Z Deselected X ...

Page 28 - Ordering Information

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 28 of 32 Ordering Information 256K × 36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM Speed (MHz) Ordering Code Package Diagram Package Type Operating Range 133 CY7C0853AV-133BBC 51-85114 172-Ball Grid Array (15 x 15 x...

Page 29 - Package Diagrams

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 29 of 32 Package Diagrams Figure 24. 172-Ball FBGA (15 x 15 x 1.25 mm) (51-85114) 51-85114-*B [+] Feedback

Page 31 - Document History Page; Synchronous Dual-Port RAM

CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 31 of 32 Document History Page Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 REV. ECN NO. Submis- sion Date Orig. of ...