Cypress CY7C0832BV - Manuals

Cypress CY7C0832BV – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C0832BV

Summary

Page 2 - Logic Block Diagram; True

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 2 of 28 Logic Block Diagram [2] A 0L –A 18L CLK L ADS L CNTEN L CNTRST L True RAM Array 19 Addr. Read Back CNTINT L Mask Register Counter/ Address Register CNT/MSK L Address Decode Dual-Ported Inter...

Page 3 - Pin Configurations

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 3 of 28 Pin Configurations Figure 1. 144-Ball BGA (Top View) CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV 1 2 3 4 5 6 7 8 9 10 11 12 A DQ17 L DQ16 L DQ14 L DQ12 L DQ10 L DQ9 L DQ9 ...

Page 5 - Pin Definitions; Byte Select Operation

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 5 of 28 Pin Definitions Left Port Right Port Description A 0L –A 18L [2] A 0R –A 18R [2] Address Inputs . ADS L [8] ADS R [8] Address Strobe Input . Used as an address qualifier. This signal should ...

Page 6 - Master Reset; Mailbox Interrupts; Table 2; Address Counter and Mask Register Operations; Retransmit

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 6 of 28 Master Reset The FLEx18 family devices undergo a complete reset by takingits MRST input LOW. The MRST input can switch asynchro-nously to the clocks. An MRST initializes the internal burstco...

Page 8 - Figure 3; Counting by Two

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 8 of 28 Retransmit Retransmit is a feature that allows the Read of a block of memorymore than once without the need to reload the initial address.This eliminates the need for external logic to store...

Page 10 - Performing a TAP Reset; Figure 5; Figure 4. Programmable Counter-Mask Register Operation

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 10 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) [21] The FLEx18 family devices incorporate an IEEE 1149.1 serialboundary scan test access port (TAP). The TAP controllerfunctions in a manner that do...

Page 12 - Electrical Characteristics

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 12 of 28 Maximum Ratings Exceeding maximum ratings [23] may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65 ° C ...

Page 13 - Switching Characteristics; Vss; ALL INPUT PULSES; OUTPUT

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 13 of 28 Figure 6. AC Test Load and Waveforms Switching Characteristics Over the Operating Range Parameter Description -167 -133 -100 Unit CY7C0837AVCY7C0830AVCY7C0831AVCY7C0832AV CY7C0837AVCY7C0830...

Page 15 - JTAG Timing and Switching Waveforms

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 15 of 28 JTAG Timing and Switching Waveforms Parameter Description CY7C0837AV/CY7C0830AVCY7C0831AV/CY7C0832AV CY7C0832BV/CY7C0833AV Unit Min Max f JTAG Maximum JTAG TAP Controller Frequency 10 MHz t...

Page 16 - Switching Waveforms; Figure 8. Master Reset

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 16 of 28 Switching Waveforms Figure 8. Master Reset Figure 9. Read Cycle [12, 30, 31, 32, 33] MRST t RSR t RS INACTIVE ACTIVE TMS TDO INT CNTINT t RSF t RSS ALLADDRESS/DATALINES ALL OTHERINPUTS t CH...

Page 17 - Figure 10. Bank Select Read

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 17 of 28 Figure 10. Bank Select Read [34, 35] Figure 11. Read-to-Write-to-Read (OE = LOW) [33, 36, 37, 38, 39] Switching Waveforms (continued) Q 3 Q 1 Q 0 Q 2 A 0 A 1 A 2 A 3 A 4 A 5 Q 4 A 0 A 1 A 2...

Page 18 - Figure 13. Read with Address Counter Advance

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 18 of 28 Figure 12. Read-to-Write-to-Read (OE Controlled) [33, 36, 38, 39] Figure 13. Read with Address Counter Advance [38] Switching Waveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t ...

Page 20 - Figure 16. Readback State of Address Counter or Mask Register

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 20 of 28 Figure 16. Readback State of Address Counter or Mask Register [43, 44, 45, 46] Switching Waveforms (continued) CNTEN CLK t CH2 t CL2 t CYC2 ADDRESS ADS A n Q x-2 Q x-1 Q n t SA t HA t SAD t...

Page 21 - CLK

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 21 of 28 Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read [47, 48, 49] Switching Waveforms (continued) t SA t HA t SW t HW t CH2 t CL2 t CYC2 CLK L R/W L A n D n t CKHZ t HD t SA A n ...

Page 22 - Figure 18. Counter Interrupt and Retransmit

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 22 of 28 Figure 18. Counter Interrupt and Retransmit [15, 42, 50, 51, 52, 53] Switching Waveforms (continued) t CH2 t CL2 t CYC2 CLK 3FFFD 3FFFF INTERNAL ADDRESS Last_Loaded Last_Loaded +1 t HCM COU...

Page 23 - Write; Read

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 23 of 28 Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58] Table 7. Read/Write and Enable Operation (Any Port) [2, 17, 59, 60, 61] Inputs Outputs Operation OE CLK CE 0 CE 1 R/W DQ 0 – DQ 17 X...

Page 24 - Ordering Information

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 24 of 28 Ordering Information 512K × 18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM Speed (MHz) Ordering Code Package Diagram Package Type Operating Range 133 CY7C0833AV-133BBC 51-85141 144-Ball...

Page 25 - Package Diagrams

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 25 of 28 32K × 18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM Speed (MHz) Ordering Code Package Diagram Package Type Operating Range 167 CY7C0837AV-167BBC 51-85141 144-Ball Grid Array (13 x 13...

Page 27 - Document History Page; Change

CY7C0837AV, CY7C0830AVCY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document #: 38-06059 Rev. *S Page 27 of 28 Document History Page Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAMDocument Numb...