Cypress CY7C0430CV - Manuals

Cypress CY7C0430CV – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C0430CV

Summary

Page 2 - Functional Description

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 2 of 37 Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz [1] , giving the device up to 10 Gb/...

Page 3 - Top Level Logic Block Diagram; Port 1 Operation-control Logic Blocks

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 3 of 37 counter is loaded with an external address when the port’s Counter Load pin (CNTLD) is asserted LOW. When the port’s Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-to- HIGH transitio...

Page 4 - Port 1 Operation-Control Logic Block Diagram; Por

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 4 of 37 Addr.Read Port 1 Operation-Control Logic Block Diagram R/W P1 CE 0P1 CE 1P1 LB P1 OE P1 UB P1 I/O 9P1 –I/O 17P1 I/O 0P1 –I/O 8P1 I/O Control Counter/ A 0P1 –A 15P1 CLK P1 CNTLD P1 CNTINC P1 CNTRST P1 16 9 9 MKLD P1 CNTINT P1 MKRD P1 Mask...

Page 5 - Pin Configuration; Top View

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 5 of 37 Pin Configuration 272-ball Grid Array (BGA) Top View Note: 4. Central Leads are for thermal dissipation only. They are connected to device V SS . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A LB P1 I/O17 P2 I/O15 P2 I/O13 P2 I/O11...

Page 6 - Selection Guide; Pin Definitions

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 6 of 37 Selection Guide CY7C0430CV –133 CY7C0430CV –100 Unit f MAX2 133 [1] 100 MHz Max Access Time (Clock to Data) 4.2 5.0 ns Max Operating Current I CC 750 600 mA Max Standby Current for I SB1 (All ports TTL Level) 200 150 mA Max Standby Curre...

Page 8 - DD; Electrical Characteristics

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 8 of 37 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.)Storage Temperature ................................ –65 ° C to + 150 ° C Ambient Temperature with Power Applied ..............................

Page 9 - AC Test Load; All Input Pulses

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 9 of 37 AC Test Load Note: 5. Test conditions: C = 10 pF. V TH = 1.5V OUTPUT C (a) Normal Load R = 50 Ω Z 0 = 50 Ω [5] 3.0V GND 90% 90% 10% t R t F 10% All Input Pulses (b) Three-State Delay V TH = 1.5V OUTPUT 5 pF R = 50 Ω Z 0 = 50 Ω (c) TAP Lo...

Page 10 - Switching Characteristics; Parameter

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 10 of 37 Switching Characteristics Over the Industrial Operating Range [6] Parameter Description CY7C0430BV and CY7C0430CV Unit –133 –100 Min. Max. Min. Max. f MAX2 [7] Maximum Frequency 133 100 MHz t CYC2 [7] Clock Cycle Time 7.5 10 ns t CH2 Cl...

Page 12 - Switching Waveforms; Master Reset

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 12 of 37 Test Clock Test Mode Select TCK TMS Test Data-InTDI Test Data-OutTDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching Waveforms Master Reset [10] Notes: 10. t S is the set-up time required for all input control signa...

Page 13 - Read Cycle

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 13 of 37 Read Cycle [12, 13, 14, 15, 16] Notes: 12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.13. CNTLD = V IL , MKLD = V IH , CNTINC = x, and MRST = CNTRST = V IH . 14. The outpu...

Page 14 - Bank Select Read

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 14 of 37 Bank Select Read [17, 18] Read-to-Write-to-Read (OE = V IL ) [19, 20, 21, 22] Notes: 17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet. ADDRE...

Page 15 - Read with Address Counter Advance

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 15 of 37 Read-to-Write-to-Read (OE Controlled) [19, 20, 21, 22] Read with Address Counter Advance [23, 24] Notes: 23. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH . 24. The “Internal Address” is equal to t...

Page 16 - Write with Address Counter Advance

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 16 of 37 Write with Address Counter Advance [24, 25] Note: 25. CE 0 = LB = UB = R/W = V IL ; CE 1 = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH. Switching Waveforms (continued) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+...

Page 17 - Counter Reset

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 17 of 37 Counter Reset [21, 26, 27] Notes: 26. CE 0 = LB = UB = V IL ; CE 1 = MRST = MKLD = MKRD = CNTRD = V IH . 27. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Switching Waveform...

Page 18 - Load and Read Address Counter

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 18 of 37 Load and Read Address Counter [28] Notes: 28. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = V IH . 29. Address in output mode. Host must not be driving address bus after time t CKLZ in next clock cycle. 30. Add...

Page 19 - Load and Read Mask Register

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 19 of 37 Load and Read Mask Register [32] Notes: 32. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =V IH . 33. This is the value of the Mask Register read out on the address lines. Switching Waveforms (continue...

Page 20 - Port 1 Write to Port 2 Read

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 20 of 37 Port 1 Write to Port 2 Read [34, 35, 36] Notes: 34. CE 0 = OE = LB = UB = CNTLD =V IL ; CE 1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =V IH . 35. This timing is valid when one port is writing, and one or more of the three other po...

Page 23 - Table 3

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 23 of 37 Master Reset The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero,...

Page 24 - Address Counter Control Operations; Figure 1; Address; Figure 1. Counter and Mask Register Read Back on Address Lines

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 24 of 37 Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port’s ...

Page 25 - Counter-Mask Register; Figure 2; Figure 2. Programmable Counter-Mask Register Operation

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 25 of 37 Counter-Mask Register The burst counter has a mask register that controls when and where the counter wraps. An interrupt flag (CNTINT) is asserted for one clock cycle when the unmasked portion of the counter address wraps around from al...

Page 26 - Table 2

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 26 of 37 address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation. 3. Readback: the internal value of either the burst counter or the ...

Page 27 - TAP Instruction Set

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 27 of 37 The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when th...

Page 28 - SPC; Debug Mode; Figure 3; MBIST Control States; Table 7; Figure 3. MBIST Debug Register Packet

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 28 of 37 number of TCK cycles depending on the TCK and CLKBIST frequency. t CYC is total number of TCK cycles required to run MBIST. SPC is the Synchronization Padding Cycles (4–6 cycles). m is a constant represents the number of read and write ...

Page 30 - JTAG/BIST TAP Controller Block Diagram; Table 4. Identification Register Definitions

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 30 of 37 JTAG/BIST TAP Controller Block Diagram Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 1h Reserved for version number Cypress Device ID (27:12) C000h Defines Cypress part number C...

Page 35 - Ordering Information; Industrial

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 35 of 37 330 IO13_P2 A4 332 IO14_P2 B4 334 IO15_P2 A3 336 IO16_P2 B3 338 IO17_P2 A2 340 IO9_P1 C9 342 IO10_P1 A10 344 IO11_P1 B9 346 IO12_P1 A9 348 IO13_P1 B8 350 IO14_P1 A8 352 IO15_P1 C6 354 IO16_P1 A7 356 IO17_P1 B7 358 IO9_P3 A15 360 IO10_P3...

Page 36 - are the trademarks of their respective holders.; Package Diagram

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 36 of 37 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a ...

Page 37 - Document History Page; Issue

CY7C0430BVCY7C0430CV Document #: 38-06027 Rev. *B Page 37 of 37 Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109906 09/10/01 SZV Change from Spec number: 38-010...