Cypress CY7C027V - Manuals - manualsarea.com

Page 2 - Pin Configurations

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 2 of 18 Pin Configurations Figure 1. 100-Pin TQFP (Top View) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 A9R A10R A11R A12R A13R A1...

Page 3 - Parameter

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 3 of 18 Pin Configurations (continued) Figure 2. 100-Pin TQFP (Top View) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 A8R A9R A10R A...

Page 4 - Write Operation; Figure 7; Read Operation; Pin Definitions; Left Port

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 4 of 18 Architecture The CY7C027V/027VN/027AV/028V andCY7037V/037AV/038V consist of an array of 32K and 64K wordsof 16 and 18 bits each of dual-port RAM cells, I/O and addresslines, and control signals (CE, OE, R/W). The...

Page 5 - Table 2; Busy; Table 3

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 5 of 18 generated to the owner. The interrupt is reset when the ownerreads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting theinterrupt. The active ...

Page 6 - CC; Electrical Characteristics

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 6 of 18 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. User guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature wi...

Page 7 - Switching Characteristics

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 7 of 18 Figure 3. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% 3 ns 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C = 30 pF V TH = 1.4V OUTPUT C = 30 pF (b) Thévenin Equivalent ...

Page 8 - Data Retention Mode

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 8 of 18 Data Retention Mode The CY7C027V/027VN/027AV/028V andCY7037V/037AV/038V are designed with battery backup inmind. Data retention voltage and supply current are guaranteedover temperature. The following rules ensur...

Page 9 - Switching Waveforms

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 9 of 18 Switching Waveforms Notes 15. R/W is HIGH for read cycles.16. Device is continuously selected CE = V IL and UB or LB = V IL . This waveform cannot be used for semaphore reads. 17. OE = V IL . 18. Address valid pr...

Page 11 - Figure 9. Semaphore Read After Write Timing, Either Side

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 11 of 18 Notes 29. CE = HIGH for the duration of the above timing (both write and read cycle).30. I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH. 31. Semaphores are reset (available to both ports) at cycle...

Page 13 - CE

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 13 of 18 Note 34. If t PS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Switching Waveforms (continued) ADDRESS MATCH t PS t BLC t BHC ADDRES...

Page 14 - Figure 15. Interrupt Timing Diagrams; Right Side Clears INT

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 14 of 18 Figure 15. Interrupt Timing Diagrams Notes 35. t HA depends on which enable pin (CE L or R/W L ) is deasserted first. 36. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last. Switching W...

Page 16 - Ordering Information

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 16 of 18 Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C027V-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027V-15AXC A100 1...

Page 17 - Package Diagram

CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document #: 38-06078 Rev. *B Page 17 of 18 Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C [+] Feedback

Page 18 - Document History Page; Worldwide Sales and Design Support; Change

Document #: 38-06078 Rev. *B Revised December 09, 2008 Page 18 of 18 All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V © Cypress Semiconductor Corporation, 2001-2008. The information contained he...