Cypress CY7B991 - Manuals - manualsarea.com

Page 2 - Signal Name; “Test Mode”

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 2 of 19 Pin Configuration Pin Definitions Signal Name IO Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected ...

Page 3 - Block Diagram Description; Phase Frequency Detector and Filter; Table 1; Skew Select Matrix; Table 2

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 3 of 19 Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputsfrom the reference frequency (REF) input and the feedback (FB)input and generate correction information to control t...

Page 4 - Test Mode; “Skew Select; Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 4 of 19 Test Mode The TEST input is a three level input. In normal systemoperation, this pin is connected to ground, enabling theCY7B991 or CY7B992 to operate as explained in “Skew Select Matrix” on page 3 . For testing purposes, any of the three...

Page 5 - Range; Commercial

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 5 of 19 Maximum Ratings Operating outside these boundaries affects the performance andlife of the device. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPowe...

Page 6 - Electrical Characteristics

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 6 of 19 Electrical Characteristics Over the Operating Range [6] CY7B991 CY7B992 Parameter Description Test Conditions Min Max Min Max Unit V OH Output HIGH Voltage V CC = Min I OH = – 16 mA 2.4 V V CC = Min, I OH =– 40 mA V CC – 0.75 V OL Output ...

Page 7 - Capacitance; Parameter; Input Capacitance; pF; AC Test Loads and Waveforms

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 7 of 19 Capacitance CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V CC = 5.0V 10 pF AC Test Loads and Wavef...

Page 8 - Switching Characteristics

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 8 of 19 Switching Characteristics Over the Operating Range [2, 13] CY7B991–2 [14] CY7B992–2 [14] Parameter Description Min Typ Max Min Typ Max Unit f NOM Operating Clock Frequency in MHz FS = LOW [1, 2] 15 30 15 30 MHz FS = MID [1, 2] 25 50 25 50...

Page 11 - AC Timing Diagrams

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 11 of 19 AC Timing Diagrams t ODCV t ODCV t REF REF FB Q OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 t RPWH t RPWL t PD t SKEWPR, t SKEW0, 1 t SKEWPR, t SKEW0, 1 t SKEW2 t SKEW2 t SKEW3, 4 t SKEW3, 4 t SKEW3, 4 t SKEW1, 3, 4 t SKEW2, 4 t...

Page 12 - Operational Mode Descriptions; Figure 2; Figure 2. Zero Skew and Zero Delay Clock Driver

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 12 of 19 Operational Mode Descriptions Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B991/992 is used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are l...

Page 13 - Figure 4. Inverted Output Connections

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 13 of 19 the FB and REF inputs and aligns their rising edges to ensurethat all outputs have precise phase alignment. Clock skews are advanced by ±6 time units (tU) when using anoutput selected for zero skew as the feedback. A wider range ofdelays...

Page 15 - Figure 8

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 15 of 19 Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative ske...

Page 16 - Ordering Information; Accuracy

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 16 of 19 Ordering Information Accuracy (ps) Ordering Code Package Type Operating Range 250 CY7B991–2JC 32-Pb Plastic Leaded Chip Carrier Commercial CY7B991–2JCT 32-Pb Plastic Leaded Chip Carrier - Tape and Reel Commercial 500 CY7B991–5JC 32-Pb Pl...

Page 17 - Military Specifications; Group A Subgroup Testing; DC Characteristics; Package Diagrams; Figure 9. 32-Pin Plastic Leaded Chip Carrier

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 17 of 19 Military Specifications Group A Subgroup Testing DC Characteristics Parameter Subgroups V OH 1, 2, 3 V OL 1, 2, 3 V IH 1, 2, 3 V IL 1, 2, 3 V IHH 1, 2, 3 V IMM 1, 2, 3 V ILL 1, 2, 3 I IH 1, 2, 3 I IL 1, 2, 3 I IHH 1, 2, 3 I IMM 1, 2, 3 I...

Page 18 - Figure 10. 32-Pin Rectangular Leadless Chip Carrier

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 18 of 19 Figure 10. 32-Pin Rectangular Leadless Chip Carrier Package Diagrams (continued) MIL-STD-1835 C-12 51-85002-*B [+] Feedback

Page 19 - Document History; Issue Date

Document Number: 38-07138 Rev. *B Revised June 22, 2007 Page 19 of 19 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registeredtrademarks referenced herein are property of the r...