Cypress CY14E256L - Manuals

Cypress CY14E256L – Manual in PDF format online.

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Summary

Page 2 - SS

CY14E256L Document Number: 001-06968 Rev. *F Page 2 of 18 Pin Configurations Figure 1. Pin Diagram: 32-Pin SOIC/DIP Pin Definitions Pin Name Alt IO Type Description A 0 –A 14 Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirectional Data IO ...

Page 3 - Figure 2; AutoStore Inhibit mode; Figure 3; Figure 2. AutoStore Mode

CY14E256L Document Number: 001-06968 Rev. *F Page 3 of 18 Device Operation The CY14E256L nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fast static RAM. Data...

Page 4 - Figure 3. AutoStore Inhibit Mode

CY14E256L Document Number: 001-06968 Rev. *F Page 4 of 18 Hardware STORE (HSB) Operation The CY14E256L provides the HSB pin for controlling andacknowledging the STORE operations. The HSB pin is used torequest a hardware STORE cycle. When the HSB pin is drivenLOW, the CY14E256L conditionally initiate...

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