Cypress CY14B108N - Manuals

Cypress CY14B108N – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY14B108N

Summary

Page 2 - PRELIMINARY; Pinouts; Top View; Top View

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 2 of 24 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44/54-Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 ...

Page 4 - Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 3; Figure 3. AutoStore Mode; Hardware STORE Operation

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 4 of 24 Device Operation The CY14B108L/CY14B108N nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a sta...

Page 5 - Software STORE

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 5 of 24 STORE operation is completed, the CY14B108L/CY14B108N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power Up) During power up or after any low power condition ...

Page 7 - Preventing AutoStore; Noise Considerations

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 7 of 24 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore ...

Page 8 - Maximum Ratings; DC Electrical Characteristics

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 8 of 24 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature .................................. –65 ° C to +150 ° C Maximum Accumulated Storage ...

Page 9 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 9 of 24 AC Test Conditions Input Pulse Levels ....................................................0V to 3VInput Rise and Fall Times (10% - 90%) ........................ <3 nsInput and Output Timing Reference Levels .................

Page 10 - AC Switching Characteristics

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 10 of 24 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [11] t RC Read Cycle ...

Page 13 - AutoStore/Power Up RECALL; RWI

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 13 of 24 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [17] Power Up RECALL Duration 20 20 20 ms t STORE [18] STORE Cycle Duration 8 8 8 ms t DELAY [19] Time Allowed to Com...

Page 14 - Software Controlled STORE/RECALL Cycle; Switching Waveforms

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 14 of 24 Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [22, 23] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/...

Page 15 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time; Write latch set

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 15 of 24 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns t SS [24, 25] So...

Page 16 - Truth Table For SRAM Operations; For x8 Configuration

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 16 of 24 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2] Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H ...

Page 17 - Ordering Information

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 17 of 24 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B108L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS20XC 51-85087 44-pin TSOP II CY14B108L-ZS20XIT 51-85087 44-pin T...

Page 19 - Part Numbering Nomenclature; Cypress

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 19 of 24 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8N - x16 Density: 108 - 8 Mb Voltage:B - 3.0V Cypress CY 14 B 108L-ZS P 20 X C T NVSRAM 14 - Auto Store + Softwa...

Page 20 - Package Diagrams

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 20 of 24 Package Diagrams Figure 15. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 ...

Page 23 - Document History Page; Date

PRELIMINARY CY14B108L, CY14B108N Document #: 001-45523 Rev. *B Page 23 of 24 Document History Page Document Title: CY14B108L/CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001-45523 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 2428826 GVCH See ECN New Data Sh...

Page 24 - Worldwide Sales and Design Support

Document #: 001-45523 Rev. *B Revised March 19, 2009 Page 24 of 24 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY CY14B108L, CY14B108N © Cy...