Page 2 - PRELIMINARY; Pinouts; Top View; Top View
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 2 of 23 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 D...
Page 3 - Pin Definitions
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 3 of 23 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name I/O Type Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A 0 – A 17 Address Inp...
Page 4 - Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 4 of 23 Device Operation The CY14B104LA/CY14B104NA nvSRAM is made up of twofunctional components paired in the same physical cell. They area SRAM memory cell and a nonvolatile QuantumTrap cell. TheSRAM memory cell operates as a st...
Page 5 - Software STORE; Table 1. Mode Selection
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 5 of 23 remains disabled until the HSB pin returns HIGH. Leave the HSBunconnected if it is not used. Hardware RECALL (Power Up) During power up or after any low power condition(V CC < V SWITCH ), an internal RECALL request is l...
Page 6 - Preventing AutoStore; Noise Considerations
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 6 of 23 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStoredisable sequence. A sequence of read operations is performedin a manner similar to the software STORE initiation. To initiatethe AutoStore d...
Page 7 - Best Practices
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 7 of 23 Best Practices nvSRAM products have been used effectively for over 15 years.While ease-of-use is one of the product’s main system values,experience gained working with hundreds of applications hasresulted in the following ...
Page 8 - Maximum Ratings; DC Electrical Characteristics
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 8 of 23 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature .................................. –65 ° C to +150 ° C Maximum Accumulated Storag...
Page 9 - AC Test Conditions; Thermal Resistance; OUTPUT
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 9 of 23 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <3 ns Input and Output Timing Reference Levels ............
Page 10 - AC Switching Characteristics
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 10 of 23 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [13] t RC Read Cycl...
Page 13 - AutoStore/Power Up RECALL; RWI
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 13 of 23 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [19] Power Up RECALL Duration 20 20 20 ms t STORE [20] STORE Cycle Duration 8 8 8 ms t DELAY [21] Time Allowed to C...
Page 14 - Software Controlled STORE/RECALL Cycle; Switching Waveforms
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 14 of 23 Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [24, 25] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STOR...
Page 15 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time; Write latch set
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 15 of 23 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns t SS [26, 27] ...
Page 16 - For x8 Configuration
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 16 of 23 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2] Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active L ...
Page 17 - Ordering Information
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 17 of 23 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B104LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104LA-ZS20XC 51-85087 44-pin TSOP II CY14B104LA-ZS20XIT 51-85087 44-...
Page 19 - Part Numbering Nomenclature; Cypress; Rev
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 19 of 23 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8 N - x16 Density: 104 - 4 Mb Voltage:B - 3.0V Cypress CY 14 B 104 L A -ZS P 20 X C T NVSRAM 14 - Auto Store +...
Page 20 - Package Diagrams
PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 20 of 23 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.73...
Page 23 - Document History Page; Worldwide Sales and Design Support; Submission
Document #: 001-49918 Rev. *A Revised March 11, 2009 Page 23 of 23 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductors. All other products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY CY14B104LA, CY14B104NA © Cypre...