Cypress CY14B104N - Manuals

Page 2 - Pinouts; Top View; Top View

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 2 of 25 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ 6 NC DQ 7 NC...

Page 3 - Pin Definitions

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 3 of 25 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name IO Type Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A 0 – A 17 Address Inputs Used to Sel...

Page 4 - Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 4 of 25 Device Operation The CY14B104L/CY14B104N nvSRAM is made up of twofunctional components paired in the same physical cell. They arean SRAM memory cell and a nonvolatile QuantumTrap cell. TheSRAM memory cell operates as a standard fast sta...

Page 6 - Noise Considerations

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 6 of 25 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStoredisable sequence. A sequence of read operations is performedin a manner similar to the software STORE initiation. To initiatethe AutoStore disable sequenc...

Page 7 - DC Electrical Characteristics

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 7 of 25 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage Time At 150 °...

Page 8 - Thermal Resistance; OUTPUT

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 8 of 25 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% - 90%)........................ <3 ns Input and Output Timing Reference Levels .................... 1.5...

Page 14 - Hardware STORE Cycle; Hardware STORE Pulse Width; Hardware STORE LOW to STORE Busy; Switching Waveforms

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 14 of 25 Hardware STORE Cycle Parameters Description CY14B104L/CY14B104N Unit Min Max t PHSB Hardware STORE Pulse Width 15 ns t HLBL Hardware STORE LOW to STORE Busy 500 ns Switching Waveforms Figure 14. Hardware STORE Cycle [21] Figure 15. Sof...

Page 15 - Truth Table For SRAM Operations; For x8 Configuration

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 15 of 25 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2] Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Out...

Page 16 - Ordering Information

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 16 of 25 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B104L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS20XI 51-85087 44-pin TS...

Page 18 - Part Numbering Nomenclature; Cypress

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 18 of 25 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8N - x16 Density: 104 - 4 Mb Voltage:B - 3.0V Cypress CY 14 B 104 L - ZS P 20 X C T NVSRAM 14 - Auto Store + Software Store ...

Page 19 - Package Diagrams; TOP VIEW

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 19 of 25 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.0...

Page 22 - Document History Page; Submission

CY14B104L, CY14B104N Document #: 001-07102 Rev. *L Page 22 of 25 Document History Page Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 431039 See ECN TUP New Data Sheet *A 489096 S...