Cypress CY14B104K - Manuals

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Manual

Manual Cypress CY14B104K

Summary

Page 2 - PRELIMINARY; Pinouts; DQ

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 2 of 31 Pinouts Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A ...

Page 3 - Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 2

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 3 of 31 Device Operation The CY14B104K/CY14B104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a st...

Page 4 - Software STORE

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 4 of 31 power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operati...

Page 5 - Preventing AutoStore; Table 2. Mode Selection

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 5 of 31 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore ...

Page 6 - Data Protection; Table 4; Note

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 6 of 31 Data Protection The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when V CC is less t...

Page 7 - Setting the Clock; Calibrating the Clock; Alarm; Watchdog Timer

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 7 of 31 must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start.While...

Page 8 - Figure 3; Figure 3. Watchdog Timer Block Diagram; Power Monitor; “AutoStore Operation”; Interrupts; Interrupt Register; Watchdog Interrupt Enable - WIE; Flags Register; “Stopping and

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 8 of 31 New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is ‘1’, writes to bits D5...

Page 9 - Figure 4. RTC Recommended Component Configuration; WDF - Watchdog Timer Flag

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 9 of 31 Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Recommended Values Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF X1 X2 Y1 C2 C1 Note: The recommended values for C1 and C2 include board t...

Page 10 - Table 4. RTC Register Map

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 10 of 31 Table 4. RTC Register Map [8] Register BCD Format Data [9] Function/Range CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0 0x7FFFF 0x3FFFF 10s Years Years Years: 00–99 0x7FFFE 0x3FFFE 0 0 0 10s Months Months Months: 01–12 0x7FFF...

Page 12 - Register; Interrupt Status/Control

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 12 of 31 Register Description CY14B104K CY14B104M 0x7FFF8 0x3FFF8 Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Sign Calibration OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the...

Page 13 - Table 5. Register Map Detail

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 13 of 31 Register Description CY14B104K CY14B104M 0x7FFF4 0x3FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M M...

Page 14 - Maximum Ratings; DC Electrical Characteristics

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 14 of 31 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage ...

Page 15 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 15 of 31 AC Test Conditions Input Pulse Levels ....................................................0V to 3VInput Rise and Fall Times (10% - 90%) ........................ <3 nsInput and Output Timing Reference Levels ................

Page 17 - AC Switching Characteristics

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 17 of 31 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [16] t RC Read Cycle ...

Page 18 - Switching Waveforms; Figure 8. SRAM Read Cycle 2: CE Controlled

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 18 of 31 Switching Waveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3, 16, 20] Figure 9. SRAM Write Cycle 1: WE Controlled [3, 19, 20, 21] Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE ...

Page 19 - Figure 10. SRAM Write Cycle 2: CE Controlled

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 19 of 31 Switching Waveforms Figure 10. SRAM Write Cycle 2: CE Controlled [3, 19, 20, 21] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled [6, 19, 20, 21, 22] Data Output Data Input Input Data Valid High Impedance Address Valid...

Page 20 - AutoStore/Power Up RECALL; RWI

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 20 of 31 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [23] Power Up RECALL Duration 20 20 20 ms t STORE [24] STORE Cycle Duration 8 8 8 ms t DELAY [25] Time Allowed to Com...

Page 21 - Software Controlled STORE and RECALL Cycle

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 21 of 31 Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [28, 29] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC ST...

Page 22 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write latch set

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 22 of 31 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns Switching Wavefo...

Page 23 - Truth Table For SRAM Operations; For x8 Configuration

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 23 of 31 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs and Outputs [2] Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active ...

Page 24 - Part Numbering Nomenclature; Cypress

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 24 of 31 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns25 - 25 ns Data Bus: K - x8 + RTCM - x16 + RTC Density: 104 - 4 Mb Voltage:B - 3.0V Cypress CY14 B 104 K ZS P 20 X C T NVSRAM 14 - AutoStor...

Page 25 - Ordering Information

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 25 of 31 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B104K-ZS20XCT 51-85087 44-pin TSOPII Commercial CY14B104K-ZS20XC 51-85087 44-pin TSOPII CY14B104K-ZS20XIT 51-85087 44-pin TSO...

Page 26 - Package Diagrams

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 26 of 31 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 ...

Page 28 - Document History Page; Date

PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 28 of 31 Document History Page Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 431039 See E...

Page 31 - Worldwide Sales and Design Support

Document #: 001-07103 Rev. *K Revised January 29, 2009 Page 31 of 31 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respectiveholders. PRELIMINARY CY14B104K, CY14B104M © C...