Cypress CY14B101NA - Manuals

Page 2 - PRELIMINARY; Pinouts; Top View; Top View

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 2 of 25 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC NC A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ ...

Page 4 - Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 4 of 25 Device Operation The CY14B101LA/CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as ...

Page 5 - Software STORE; Table 2. Mode Selection

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 5 of 25 During any STORE operation, regardless of how it is initiated, the CY14B101LA/CY14B101NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B10...

Page 6 - Preventing AutoStore; Noise Considerations

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 6 of 25 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStor...

Page 7 - Maximum Ratings; DC Electrical Characteristics

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 7 of 25 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage...

Page 8 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 8 of 25 AC Test Conditions Input Pulse Levels .................................................... 0V to 3VInput Rise and Fall Times (10% - 90%)........................ <3 nsInput and Output Timing Reference Levels ...............

Page 9 - AC Switching Characteristics

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 9 of 25 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [15] t RC Read Cycle...

Page 12 - AutoStore/Power Up RECALL; RWI

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 12 of 25 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [27] Power Up RECALL Duration 20 20 20 ms t STORE [23] STORE Cycle Duration 8 8 8 ms t DELAY [24] Time Allowed to C...

Page 13 - Software Controlled STORE/RECALL Cycle; Switching Waveforms

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 13 of 25 Software Controlled STORE/RECALL Cycle Parameters [27, 28] Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle Time 20 25 45 ns t SA Address Setup Time 0 0 0 ns t CW Clock Pulse W...

Page 14 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time; Write latch set

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 14 of 25 Hardware STORE Cycle Parameters Description 20ns 25ns 45ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns t SS [29, 30] Sof...

Page 16 - Ordering Information; Commercial

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 16 of 25 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B101LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS20XC 51-85087 44-pin TSOP II CY14B101LA-BA20XCT 51-85128 48-...

Page 19 - Part Numbering Nomenclature; Cypress; Rev

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 19 of 25 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8N - x16 Density: 101 - 1 Mb Voltage:B - 3.0V Cypress CY 14 B 101L A-ZS 20 X C T NVSRAM 14 - AutoStore + Softw...

Page 20 - Package Diagrams

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 20 of 25 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.73...

Page 24 - Document History Page; Date

PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 24 of 25 Document History Page Document Title: CY14B101LA/CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 2050747 See ECN UNC/PYRS New D...

Page 25 - Worldwide Sales and Design Support

Document #: 001-42879 Rev. *B Revised January 29, 2009 Page 25 of 25 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY CY14B101LA, CY14B101NA ...