Cypress 37000 CPLD - Manuals

Cypress 37000 CPLD – Manual in PDF format online.

Manuals:

Manual

Manual Cypress 37000 CPLD

Summary

Page 2 - Selection Guide; General Information; Speed Bins; PD

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 2 of 64 Selection Guide 5.0V Selection Guide General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t PD ) Speed (f MAX ) CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.5 167 CY37192 192 5 120 7.5 154 CY3...

Page 3 - Architecture Overview of Ultra37000 Family; Programmable Interconnect Matrix; Warp; Logic Block; Figure 1; Device

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 3 of 64 Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interco...

Page 4 - Product Term Allocator; Product Term Steering; Figure 1. Logic Block with 50% Buried Macrocells

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 4 of 64 Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conser- vation. The logic block mode is set by the user on a logic block by logic block basis. Product Term ...

Page 5 - Bus Hold Capabilities on all I/Os; Understanding Bus-Hold—A Feature of Cypress CPLDs; FROM PTM

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 5 of 64 The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output...

Page 6 - Clocking; Dedicated Inputs/Clocks; Timing Model; Figure 5; Figure 3. Input Macrocell

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 6 of 64 Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks. Dedicated Inp...

Page 7 - JTAG and PCI Standards; PCI Compliance; Development Software Support; Professional; Enterprise; COMBINATORIAL SIGNAL

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 7 of 64 JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output...

Page 8 - Third-Party Programmers

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 8 of 64 The third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the I...

Page 9 - Logic Block Diagrams; PIM

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 9 of 64 Logic Block Diagrams CY37032/CY37032V LOGIC BLOCK B LOGIC BLOCK A 36 16 36 16 Input Clock/ Input 16 I/Os 16 I/Os I/O 0 − I/O 15 I/O 16 − I/O 31 4 4 4 16 16 TDITCKTMS TDO JTAG TapController 1 PIM JTAG EN LOGIC BLOCK D LOGIC BLOCK C LOGI...

Page 14 - V Device Electrical Characteristics

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 14 of 64 5.0V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.)Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied ....

Page 17 - Switching Characteristics

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 17 of 64 Parameter [11] V X Output Waveform—Measurement Level t ER(–) 1.5V t ER(+) 2.6V t EA(+) 1.5V t EA(–) V the (d) Test Waveforms V OH V X 0.5V V OL V X 0.5V V X V OH 0.5V V X V OL 0.5V Switching Characteristics Over the Operating Range [1...

Page 21 - Latched Output; Switching Waveforms

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 21 of 64 Registered Output with Product Term Clocking Input Going Through the Array Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register Latched Output Switching Waveforms (continued) t SPT INPUT PRODUCT TERM...

Page 24 - Power Consumption

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 24 of 64 Power Consumption Typical 5.0V Power ConsumptionCY37032 CY37064 0 1 0 2 0 3 0 4 0 5 0 6 0 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 F r e q u e n c y ( M H z ) Icc (mA) H ig h S p e e d L o w P o w e r The typical pattern is a 16-bit up counter, ...

Page 25 - Typical 5.0V Power Consumption

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 25 of 64 CY37128 CY37192 Typical 5.0V Power Consumption (continued) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 F r e q u e n c y ( M H z ) Ic c (mA) L o w P o w e r H ig h S p e e d The typical pa...

Page 28 - Typical 3.3V Power Consumption

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 28 of 64 CY37064V CY37128V Typical 3.3V Power Consumption (continued) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 F r e q u e n c y ( M H z ) Icc ( m A ) L o w P o w e r H ig h S p e e d The typical pattern is a 16-...

Page 31 - Pin Configurations; GN; DO; GND

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 31 of 64 Pin Configurations [20] 44-pin TQFP (A44) Top View I/O 2 GN D V CCO I/O 3 I/O 4 I/O 1 I/O 0 I/O 29 I/O 30 I/O 31 I/O 28 I/O 27 /TDI I/O 26 I/O 25 I/O 24 CLK 1 /I 4 GNDI 3 CLK 3 /I 2 I/O 23 I/O 22 I/O 21 GND I/O 20 V CC I/O 18 I/O 17 I...

Page 43 - V Ordering Information

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 43 of 64 64 154 CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack Commercial CY37064P44-154JC J67 44-Lead Plastic Leaded Chip Carrier CY37064P84-154JC J83 84-Lead Plastic Leaded Chip Carrier CY37064P100-154AC A100 100-Lead Thin Quad Flat Pack C...

Page 47 - V Ordering Information

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 47 of 64 64 143 CY37064VP44-143AC A44 44-Lead Thin Quad Flatpack Commercial CY37064VP44-143AXC A44 44-Lead Lead Free Thin Quad Flatpack CY37064VP48-143BAC BA50 48-Ball Fine-Pitch Ball Grid Array CY37064VP100-143AC A100 100-Lead Thin Quad Flatp...

Page 49 - Package Diagrams

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 49 of 64 Package Diagrams 51-85064- * B 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 51-85003- * A 44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67 [+] Feedback

Page 50 - 4-Lead Ceramic Leaded Chip Carrier Y67

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 50 of 64 Package Diagrams (continued) 44-Lead Ceramic Leaded Chip Carrier Y67 51-80014 -** [+] Feedback

Page 52 - 4-Lead Ceramic Leaded Chip Carrier Y84

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 52 of 64 Package Diagrams (continued) 84-Lead Ceramic Leaded Chip Carrier Y84 51-80095- * A [+] Feedback

Page 56 - DETAIL A

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 56 of 64 Package Diagrams (continued) SEATING PLANE DIMENSION IN MM (INCH) 2.79(.110) 2.03(.080) 0.500(.020) 0.050(.002) (.020 ±.008) 0.51 ±0.20 (.006 ±.001) 0.15 ±0.02 TYP. 0.300(.012) TYP. 0.650(.0256) (1.228 ±.010) 31.20 ±0.25 (1.102 ±.004)...

Page 63 - Range

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 63 of 64 Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143B AC) Range Ambient Temperature [2] Junction Temperature V CC Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.16V [+] Feedback

Page 64 - Document History Page; Issue

Ultra37000 CPLD Family Document #: 38-03007 Rev. *E Page 64 of 64 Document History Page Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Document Number: 38-03007 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106272 04/18/01 SZV Change from Spec number:...