Intel 845 - Manual

Intel 845

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Table of Contents:

  • Page 3 – Contents
  • Page 7 – Figures
  • Page 8 – Revision History
  • Page 9 – Note
  • Page 10 – System Block Diagram
  • Page 11 – Introduction; Terminology and Notations; Table 1. General Terminology
  • Page 12 – Table 2. Data Type Notation
  • Page 13 – Documents
  • Page 14 – 45 Chipset System Architecture
  • Page 15 – System Bus Interface; System Bus Error Checking
  • Page 16 – System Memory Interface; Table 4. Memory Capacity; Interface; only
  • Page 17 – MCH Clock Ratio Table
  • Page 18 – Interrupts
  • Page 19 – Signal; AGP
  • Page 20 – MCH Simplified Block Diagram
  • Page 21 – System Bus Signals
  • Page 23 – SDR SDRAM Interface Signals
  • Page 24 – AGP Interface Signals; AGP Addressing Signals
  • Page 25 – AGP Flow Control Signals
  • Page 26 – AGP Strobes Signals; Signals
  • Page 28 – Clocks, Reset, and Miscellaneous Signals
  • Page 29 – Voltage Reference and Power Signals
  • Page 30 – Reset States During Reset
  • Page 31 – Register; Terminology
  • Page 32 – PCI Bus Configuration Space Access; Note that the primary PCI bus; MCH Internal Device Assignments
  • Page 33 – Standard PCI Bus Configuration Mechanism; PCI Bus 0 Configuration Mechanism
  • Page 34 – Primary PCI and Downstream Configuration Mechanism; I/O Mapped Registers; CONF_ADDR—Configuration Address Register
  • Page 36 – CONF_DATA—Configuration Data Register; Memory-Mapped Register Space; Table 7. Memory-mapped Register Address Map
  • Page 37 – DRAMWIDTH—DRAM Width Register
  • Page 39 – CKESTR—Strength Control Register (SCKE Signal Group)
  • Page 41 – CKSTR—Strength Control Register (Clock Signal Group)
  • Page 45 – VID—Vendor Identification Register (Device 0); DID—Device Identification Register (Device 0)
  • Page 48 – RID—Revision Identification Register (Device 0)
  • Page 49 – MLT—Master Latency Timer Register (Device 0)
  • Page 50 – APBASE—Aperture Base Configuration Register (Device 0)
  • Page 51 – SVID—Subsystem Vendor Identification (Device 0)
  • Page 53 – DRA—DRAM Row Attribute Registers (Device 0)
  • Page 56 – DRC—DRAM Controller Mode Register (Device 0)
  • Page 58 – DERRSYN—DRAM Error Syndrome Register (Device 0); EAP—Error Address Pointer Register (Device 0)
  • Page 60 – Figure 2. PAM Register Attributes
  • Page 61 – Table 9. PAM Register Attributes; Routing of
  • Page 62 – Extended System BIOS Area (E0000h–EFFFFh); FDHC—Fixed DRAM Hole Control Register (Device 0)
  • Page 65 – ACAPID—AGP Capability Identifier Register (Device 0)
  • Page 73 – TOM—Top of Low Memory Register (Device 0)
  • Page 74 – MCHCFG—MCH Configuration Register (Device 0)
  • Page 76 – ERRCMD—Error Command Register (Device 0)
  • Page 79 – SKPD—Scratchpad Data Register (Device 0)
  • Page 81 – VID1—Vendor Identification Register (Device 1); DID1—Device Identification Register (Device 1)
  • Page 84 – RID1—Revision Identification Register (Device 1); BCC1—Base Class Code Register (Device 1)
  • Page 85 – MLT1—Master Latency Timer Register (Device 1); PBUSN1—Primary Bus Number Register (Device 1)
  • Page 86 – SBUSN1—Secondary Bus Number Register (Device 1); SUBUSN1—Subordinate Bus Number Register (Device 1)
  • Page 90 – MBASE1—Memory Base Address Register (Device 1); MLIMIT1—Memory Limit Address Register (Device 1)
  • Page 93 – ERRCMD1—Error Command Register (Device 1)
  • Page 97 – System Address Map; Memory Address Ranges; Figure 3. Addressable Memory Space
  • Page 98 – Figure 4. DOS Compatible Area Address Map
  • Page 99 – VGA and MDA Memory Space
  • Page 100 – PAM Memory Spaces; ISA expansion region; ISA Hole Memory Space
  • Page 101 – TSEG SMM Memory Space
  • Page 102 – AGP Memory and Prefetchable Memory; Hub Interface Subtractive Decode; AGP Memory Address Ranges
  • Page 103 – AGP DRAM Graphics Aperture; System Management Mode (SMM) Memory Range
  • Page 104 – SMM Space Definition; Table 11. SMM Space Address Ranges; SMM Space Restrictions
  • Page 105 – MCH Decode Rules and Cross-Bridge; Hub Interface Decode Rules
  • Page 106 – AGP Interface Decode Rules; Cycles Initiated Using AGP FRAME# Protocol
  • Page 107 – Functional; Bus; Dynamic Bus Inversion
  • Page 108 – System Bus Interrupt Delivery
  • Page 109 – Single Data Rate (SDR) SDRAM Interface Overview; Table 12. Supported DIMM Configurations
  • Page 110 – Configuration Mechanism For DIMMs; Memory Detection and Initialization; Memory Register Programming; Table 13. Data Bytes on DIMM Used for Programming DRAM Registers
  • Page 111 – Memory Address Translation and Decoding; Table 14. Address Translation and Decoding
  • Page 112 – DRAM Performance Description; AGP Interface Overview; AGP Target Operations
  • Page 114 – AGP Transaction Ordering; AGP Signal Levels; x AGP Protocol; Writes
  • Page 115 – Table 16. Data Rate Control Bits; AGP FRAME# Transactions on AGP; MCH Initiator and Target Operations; Table 17. PCI Commands Supported by the Intel
  • Page 116 – target
  • Page 117 – MCH Retry/Disconnect Conditions; Delayed Transaction; Power and Thermal Management; Processor Power State Control
  • Page 118 – Sleep State Control; MCH Clocking
  • Page 119 – Electrical; Absolute Maximum Ratings; Table 18. Absolute Maximum Ratings; Characteristics; Table 19. Power Characteristics
  • Page 120 – Groups
  • Page 122 – Table 21. DC Characteristics
  • Page 125 – Ballout and Package Information
  • Page 126 – 2845 MCH Ballout Diagram (Top View—Left Side)
  • Page 127 – 2845 MCH Ballout Diagram (Top View—Right Side)
  • Page 128 – 2845 MCH Ballout Listed Alphabetically by Signal Name
  • Page 134 – Package Mechanical Information
  • Page 137 – Testability; Figure 10. XOR Tree Chain; XOR Test Mode Initialization
  • Page 138 – Chains; Table 23. XOR Chain 0
  • Page 140 – Table 24. XOR Chain 1
  • Page 141 – Table 25. XOR Chain 2
  • Page 142 – Table 26. XOR Chain 3
  • Page 143 – Table 27. XOR Chain 4
  • Page 144 – Table 28. XOR Chain 5
  • Page 146 – Table 29. XOR Chain 6
  • Page 147 – Table 30. XOR Chain 7
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Intel

®

845 Chipset: 82845

Memory Controller Hub (MCH)
for SDR

Datasheet




January 2002











Document Number:

290725-002

R

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Summary

Page 3 - Contents

R Intel ® 82845 MCH for SDR Datasheet 3 Contents 1 Introduction ........................................................................................................................ 11 1.1 Terminology and Notations .....................................................................................

Page 7 - Figures

R Intel ® 82845 MCH for SDR Datasheet 7 Figures Figure 1. Intel ® MCH Simplified Block Diagram ................................................................. 20 Figure 2. PAM Register Attributes ..................................................................................... 60 Figure 3. Add...

Page 8 - Revision History

R 8 Intel ® 82845 MCH for SDR Datasheet Revision History Revision Number Description Date -001 Initial Release. September 2001 -002 • Changed the document name to add the term “for SDR”. • DWTC—DRAM Write Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device ...

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