Page 3 - Contents
R AC ’97 Programmer’s Reference Manual 3 Contents 1 Introduction.......................................................................................................................... 7 1.1 About This Document ..........................................................................................
Page 5 - Figures; Tables
R AC ’97 Programmer’s Reference Manual 5 Figures Figure 1. Block Diagram of Platform Chipset with Intel ® ICH5 Component ...................... 13 Figure 2. Intel ® ICH5 AC ’97 Controller Connection to Its Companion Codecs ................ 14 Figure 3. Generic Form of Buffer Descriptor (One Entry in...
Page 6 - Revision History
R 6 AC ’97 Programmer’s Reference Manual Revision History Revision Number Description Revision Date -001 Initial Release. April 2003
Page 7 - Introduction; About This Document; Table 1. Applicable Components
Introduction R AC ’97 Programmer’s Reference Manual 7 1 Introduction 1.1 About This Document This document was prepared to assist Independent Hardware and Software Vendors (IHVs and ISVs) in supporting the Intel ® I/O controller hub (ICH5) AC ’97 controller feature set. This document also applies to...
Page 9 - Reference Documents and Information Sources
Introduction R AC ’97 Programmer’s Reference Manual 9 Devi ce Nam e Vendor ID Devi ce I D S ubsystem V endor ID S ubsystem Devi ce ID Base Cl ass Code S ub-Cl ass Code P rog. I n terface Revi si on I D Bu s Nu m b er (P CI A ddr ) Devi ce Num b er Funct ion N u m b er Mic ros of t PN P Devi ce Node ...
Page 11 - Overview; ICH5 AC ’97 Controller Compatibility
Overview R AC ’97 Programmer’s Reference Manual 11 2 Overview In this document, “ICH5” stands for I/O Controller Hub 5. The ICH5 provides an AC ’97-compliant controller. References to the “AC ’97 Component Specification” refer to the Audio Codec ’97 Specification , Revision 2.1, Revision 2.2, and Re...
Page 12 - Table 2. Audio Features Distribution Matrix
Overview R 12 AC ’97 Programmer’s Reference Manual Table 2. Audio Features Distribution Matrix AC ’97 Audio Controller Features Intel ® ICH Intel ® ICH2 Intel ® ICH3 Intel ® ICH4 Intel ® ICH5 16 bits Stereo PCM Output ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ 16 bits Stereo PCM Input ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧ ⌧...
Page 13 - Process
Overview R AC ’97 Programmer’s Reference Manual 13 Figure 1. Block Diagram of Platform Chipset with Intel ® ICH5 Component Intel® ICH5 USB 2.0 (Supports 6 USB ports) System Management (TCO) IDE-Primary GPIO SMBus 2.0/I 2 C IDE-Secondary Power Management PCI Bus ... Clock Generators SL O T S L O T AG...
Page 14 - ICH5 AC ’97 Controller Connection to Its Companion Codecs; Third AC ’97 Component Specification Revision 2.1,
Overview R 14 AC ’97 Programmer’s Reference Manual Figure 2. Intel ® ICH5 AC ’97 Controller Connection to Its Companion Codecs Intel ® ICH Digital Controller Primary Codec AC '97/AC '97 2.x/AMC '97 RESET# SDATA_OUT SYNC BIT_CLK SDATA_IN_2 SDATA_IN_1 SDATA_IN_0 AC '97/MC '97 2.x/AMC '97 AC '97/AC '97...
Page 15 - Dedicated S/P DIF DMA Output Channel; Memory Map Status and Control Registers
Overview R AC ’97 Programmer’s Reference Manual 15 2.1.2 Dedicated S/P DIF DMA Output Channel The ICH5 controller provides a dedicated DMA engine with the capability of outputting either PCM or AC-3 data to the S/P DIF link for pass-through to an external CE audio decoder. This capability allows for...
Page 16 - Second Independent Input DMA Engines; Requirements
Overview R 16 AC ’97 Programmer’s Reference Manual 2.1.5 Second Independent Input DMA Engines The ICH5 continues to provide two sets of input DMA engines that allow for the secondary or tertiary codecs to provide recording PCM data streams on the primary codec while simultaneously providing recordin...
Page 17 - Intel; ICH5 AC ’97 Initialization; Reset; read; Topology; The following are the loading rules for ICH5
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 17 3 Intel ® ICH5 AC ’97 Controller Theory of Operation The ICH5 AC ’97 digital controller (DC) interface is an implementation of the AC-link, with additional features to support the transaction and device power...
Page 18 - BIOS PCI Configuration; Table 3. Audio Registers
Intel® ICH5 AC ’97 Controller Theory of Operation R 18 AC ’97 Programmer’s Reference Manual Drivers can distribute output and input data in appropriate slots associated with available codec(s). For example a 6-channel data stream can be separated into three, 2-channel codec streams as long as the co...
Page 19 - Table 4. Modem Registers; Hardware Interrupt Routing
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 19 Table 4. Modem Registers Device 31 Function 6 Modem Offset Register Default Comments 04h-05h Command (COM) 0000h Bit 2: Bus Master Enable Bit 0: I/O Space Enable 10h-13h Native Audio Mixer Base Address 000000...
Page 20 - Engines; Buffer Descriptor List; no samples; Figure 3. Generic Form of Buffer Descriptor (One Entry in the List)
Intel® ICH5 AC ’97 Controller Theory of Operation R 20 AC ’97 Programmer’s Reference Manual 3.2 DMA Engines The ICH5 AC ’97 controller uses a scatter gather mechanism to access memory. There are five, 16-bit DMA engines for Audio: 2 PCM Stereo In, 2 MIC mono in, and S/P DIF Out. There is one, 20-bit...
Page 21 - DMA Initialization; Figure 4. Buffer Descriptor List
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 21 Table 6. BD Control and Length (DWORD 1: 04-07h) Bit Description 31 Interrupt on Completion (IOC) 1= Enable , 0 = Disable. When this it is set, it means the controller should issue an interrupt upon completio...
Page 22 - Table 7. Audio Descriptor List Base Address; Table 8. Modem Descriptor List Base Address; Table 9. Audio Last Valid Index
Intel® ICH5 AC ’97 Controller Theory of Operation R 22 AC ’97 Programmer’s Reference Manual The following steps describe the driver initialization process for a single DMA engine. The same process should be repeated for each DMA engine. 1. Create the buffer descriptor list structure in non-pageable ...
Page 23 - Table 10. Modem Last Valid Index; DMA Steady State Operation
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 23 Table 10. Modem Last Valid Index Modem Last Valid Index (LVI) I/O Address: Line IN MBAR + 05h (MILVI) Line OUT MBAR + 15h (MOLVI), 5. After LVI registers are updated, software sets the run bit in the control ...
Page 24 - Stopping Transfers; FIFO Underrun
Intel® ICH5 AC ’97 Controller Theory of Operation R 24 AC ’97 Programmer’s Reference Manual // Advance tail to next value tail++; } 3.2.4 Stopping Transfers There are two ways that DMA transfers can be stopped. 1. By simply turning off the Bus Master run/pause bit. This will halt the current DMA tra...
Page 25 - Arbitration; Memory Organization of Data
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 25 2. As a result of the DMA engine reaching the Last Valid Index, no further access to memory, therefore FIFO will not drain. This condition is an error if software is not able to update the descriptor list bef...
Page 26 - Organization; over Next Frame
Intel® ICH5 AC ’97 Controller Theory of Operation R 26 AC ’97 Programmer’s Reference Manual 3.4.3 FIFO Organization The ICH5 AC ’97 controller supports 16-bit samples on all channels except PCM Out, which also supports 20-bit samples. Data will be written to the FIFO in sample pairs following the or...
Page 27 - Next Frames; Table 11. FIFO Summary; Multiple Codec/Driver Support
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 27 Figure 7. Incompatible Implementation of Sample Rate Conversion with Repeating Slots over Next Frames Frame n Frame n + 1 Frame n + 2 Frame n + 3 CMD DATA MDM CDC RSVD RSVD RSVD RSVD RSVD RSVD I/O Control CMD...
Page 28 - Table 12. SDM Register Description; Codec Register Shadowing; must
Intel® ICH5 AC ’97 Controller Theory of Operation R 28 AC ’97 Programmer’s Reference Manual Table 12. SDM Register Description Bit Type Reset Description 7:6 RW 00 PCM In 2, Microphone In 2 Data In Line (D21L): When the SE bit is set, these bits indicate which SDATA_IN line should be used by the har...
Page 29 - Codec Access Synchronization; Data Request Synchronization in Audio Split
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 29 Shadowing in memory is effective as long as the codec itself does not change the value of the registers. Therefore, the status of the GPIOs configured as inputs on the most recent frame is accessible to softw...
Page 30 - Power Management; Topologies; Table 13. Dual Codecs Topologies
Intel® ICH5 AC ’97 Controller Theory of Operation R 30 AC ’97 Programmer’s Reference Manual 3.6 Power Management Power management of the driver/codec interaction requires careful sequencing in the ICH5 AC ’97 environment. In the ICH5 AC ’97 environment it is possible to have two drivers sharing the ...
Page 31 - Tertiary Codec Topologies; Power Management Transition Maps
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 31 Configuration 5 is a two-codec audio topology. In this configuration concerns are on the proper power down sequence. However, no driver interaction is expected as only the audio driver executes power manageme...
Page 34 - Power Management Topology Considerations; Determining the Presence of Secondary and Tertiary Codecs
Intel® ICH5 AC ’97 Controller Theory of Operation R 34 AC ’97 Programmer’s Reference Manual Table 17. Power State Mapping for Modem in Dual Codec Desktop Transition PR<A:D> + MLNK (other power control (PRx) bits do not apply for Intel ® ICH5 implementation) +12 +5 from +12 +3.3 Digital +3.3 Va...
Page 35 - Determining the Presence of a Modem Function; Resume Context Recovery
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 35 3.6.3.2 Determining the Presence of a Modem Function In the case of an AMC configuration, only the primary codec ready bit will be indicated. In order to determine proper power down configuration, the audio d...
Page 36 - Primary Audio Requested to D3
Intel® ICH5 AC ’97 Controller Theory of Operation R 36 AC ’97 Programmer’s Reference Manual 3.6.5.1 Primary Audio Requested to D3 The audio power management procedure attempting to get the audio codec to D3 state. If MD3 == true // (sleeping?) { Audio_Power_Manage_Reg = D3 + PR4 + PR5; // yes, sleep...
Page 37 - Audio Primary Requested to D0; ICH5 AC ’97 Warm Reset#
Intel® ICH5 AC ’97 Controller Theory of Operation R AC ’97 Programmer’s Reference Manual 37 3.6.5.4 Audio Primary Requested to D0 The audio power management procedure will attempt to get the audio codec to D0 state. AD3 = false // set to "audio awake" // Setting the flag first avoid race con...
Page 39 - Surround Audio Support; Determine Codec’s Audio Channels; Table 18. Extended Audio ID Register; Table 19. Single Codec Audio Channel Distribution
Surround Audio Support R AC ’97 Programmer’s Reference Manual 39 4 Surround Audio Support The AC ’97 Component Specification allows for up to six channels of audio supported in the AC- link. The audio device driver must determine the number of audio channels available in the codec(s) and properly en...
Page 40 - Table 20. Multiple Codec Audio Channel Distribution; Table 21. CM 4/6 –PCM Channels Capability Bits
Surround Audio Support R 40 AC ’97 Programmer’s Reference Manual Table 20. Multiple Codec Audio Channel Distribution Split Audio Codec Configuration Primary Secondary Tertiary Total Channels L/R - - 2 L/R S-L/R - 4 L/R S-L/R; C/LFE - 6 L/R S-L/R C/LFE 6 Legend: L/R: Left Stereo Channel (Slot 3); Rig...
Page 43 - Table 23. Sample Capabilities; Table 24. PCM Out Mode Selector
20-Bits PCM Support R AC ’97 Programmer’s Reference Manual 43 5 20-Bits PCM Support The ICH5 AC ’97 controller provides support for 16- or 20-bit PCM out. Software can determine if 20-bit samples are supported in the controller by reading the sample capabilities bits in GLOB_STA registers as follows...
Page 47 - Support for Double Rate Audio
Support for Double Rate Audio R AC ’97 Programmer’s Reference Manual 47 7 Support for Double Rate Audio The ICH5 AC’97 controller has the capability of supporting a stereo 96 kHz stream using the AC’97 Double Rate Audio (DRA) support. This capability is enabled by programming the controller to use f...
Page 49 - Link Topology Determination; Table 26. Topology Descriptor
Independent Input Channels Capability R AC ’97 Programmer’s Reference Manual 49 8 Independent Input Channels Capability ICH5 AC ’97 controller provides capability for two DMA channels dedicated to independent PCM and Microphone audio streams. These allow improved features that enable applications su...
Page 50 - Table 28. Codec Ready Bits; Table 29. MMBAR: Mixer Base Address Register
Independent Input Channels Capability R 50 AC ’97 Programmer’s Reference Manual Bit Description 11 Reserved 3 Steer Enable (SE): When set, the SDATA_IN lines are treated separately and not OR’d together before being sent to the DMA engines. When cleared, the SDATA_IN lines are OR’d together, and the...
Page 51 - Intel; Robust Host-Based Generation of a Synchronous
Intel® ICH5 AC ’97 Modem Driver R AC ’97 Programmer’s Reference Manual 51 9 Intel ® ICH5 AC ’97 Modem Driver The AC ’97 Component Specification allows for a modem codec to be connected to the AC-link interface. This allows for the development of a software stack that provides modem functionality, i....
Page 52 - Spurious Data Algorithm; ICH5 AC ’97 Spurious Data Implementation
Intel® ICH5 AC ’97 Modem Driver R 52 AC ’97 Programmer’s Reference Manual The first invocation of the host based modem task provides an initial buffer and one or more buffers of spurious data (henceforth, spurious buffers). The task chooses or computes each of the spurious buffer(s) based on signal ...
