Intel 324632-003 - Manual

Intel 324632-003

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Table of Contents:

  • Page 2 – Legal
  • Page 3 – Revisions
  • Page 4 – Content
  • Page 18 – NOTE: This page intentionally left blank.
  • Page 19 – Register and Bit References; Byte and Bit Designations
  • Page 20 – Memory Alignment Terminology
  • Page 21 – Architectural Overview; External Architecture
  • Page 22 – System Interface
  • Page 23 – Flash Memory Interface; Software Watchdog
  • Page 24 – LEDs; DMA Addressing
  • Page 25 – Ethernet Addressing
  • Page 26 – Interrupt Control and Tuning; Hardware Acceleration Capability
  • Page 27 – Jumbo Frame Support; Buffer and Descriptor Structure
  • Page 28 – Multiple Transmit Queues
  • Page 29 – Power Up State
  • Page 30 – Global Reset and General Configuration; Receive Initialization
  • Page 31 – Initialize the Receive Control Register; Transmit Initialization
  • Page 32 – Dynamic Queue Enabling and Disabling; Link Setup Mechanisms and Control/Status; PHY Initialization
  • Page 37 – Reset Operation
  • Page 41 – PHY Behavior During a Manageability Session:
  • Page 42 – Initialization of Statistics
  • Page 43 – EEPROM and Flash Interface; EEPROM Device; Software Accesses
  • Page 44 – Signature and CRC Fields
  • Page 45 – Protected EEPROM Space; Initial EEPROM Programming
  • Page 46 – Activating the Protection Mechanism; Non Permitted Accesses to Protected Areas in
  • Page 49 – Flash Interface Operation
  • Page 50 – Flash Write Control; Shared EEPROM; EEPROM Deadlock Avoidance
  • Page 51 – EEPROM Map Shared Words; Shared FLASH
  • Page 52 – Flash Access Contention; EEPROM Map
  • Page 54 – Hardware Accessed Words
  • Page 63 – NC-SI and PCIe* Completion Timeout Configuration
  • Page 72 – Management Hardware Configuration Control (Word
  • Page 74 – End of RO Area (Word 2Ch; Main Setup Options PCI Function 0 (Word 30h)
  • Page 76 – Configuration Customization Options PCI Function 0 (Word 31h)
  • Page 78 – Configuration Customization Options PCI Function 1 (Word 35h); Configuration Customization Options PCI Function 2 (Word 39h); Configuration Customization Options PCI Function 3 (Word 3Bh); iSCSI Boot Configuration Offset (Word 3Dh); iSCSI Module Structure
  • Page 81 – Manageability Control Sections; Sideband Configuration Structure
  • Page 83 – Flex TCO Filter Configuration Structure
  • Page 85 – NC-SI Microcode Download Structure
  • Page 86 – NC-SI Configuration Structure
  • Page 87 – Common Firmware Pointer
  • Page 88 – Manageability Capability/Manageability Enable (Word; Pass Through Pointers; Flex TCO Filter Configuration Pointer (Word 58h)
  • Page 90 – PT LAN Configuration Structure
  • Page 92 – LAN0 UDP Flex Filter Ports 0:15 MFUTP Registers
  • Page 97 – ARP Response IPv4 Address 0 LSB (Offset 43h)
  • Page 98 – Software Owned EEPROM Words
  • Page 101 – Transmit Data Flow
  • Page 102 – Receive Data Flow
  • Page 103 – Packet Address Filtering; Receive Data Storage
  • Page 104 – Legacy Receive Descriptor Format; Length Field
  • Page 105 – Receive Descriptor Status Field
  • Page 107 – Receive Descriptor Errors Field
  • Page 109 – VLAN Tag Field; Advanced Receive Descriptors; Packet Buffer Address
  • Page 111 – Packet Type
  • Page 112 – Packet Checksum
  • Page 113 – RSS Hash Value
  • Page 114 – Extended Errors
  • Page 115 – Packet Buffer (Number of Bytes Exists in the Host
  • Page 116 – Receive UDP Fragmentation Checksum; Receive Descriptor Fetching
  • Page 117 – Receive Descriptor Write-Back; Receive Descriptor Packing; Receive Descriptor Ring Structure
  • Page 119 – Multiple Receive Queues
  • Page 120 – Queuing for Virtual Machine Devices (VMDq); Association Through MAC Address
  • Page 121 – Association Through MAC Address + RSS; Association through VLAN tag ID
  • Page 122 – Multiple Receive Queues & Receive-Side Scaling; RSS Hash Function
  • Page 124 – Hash for IPv4 with TCP
  • Page 125 – Hash for IPv4 with UDP; Indirection Table
  • Page 126 – Support for Multiple Processors; RSS Verification Suite
  • Page 127 – Header Splitting and Replication
  • Page 130 – Receive Packet Checksum Offloading
  • Page 131 – MAC Address Filter
  • Page 132 – IPv6 Extension Headers
  • Page 133 – Packet Transmission
  • Page 134 – Transmit Data Storage
  • Page 135 – Transmit Descriptors; Legacy Transmit Descriptor Format
  • Page 136 – Transmit Descriptor Write Back Format; Length
  • Page 139 – Transmit Descriptor Status Field Format; Transmit Descriptor Special Field Format
  • Page 140 – Advanced Transmit Context Descriptor
  • Page 142 – Advanced Transmit Data Descriptor
  • Page 143 – DCMD
  • Page 144 – STA; IDX; PAYLEN; Transmit Descriptor Ring Structure
  • Page 146 – Transmit Descriptor Fetching; Transmit Descriptor Write-Back
  • Page 147 – TCP Segmentation
  • Page 148 – Assumptions; TCP Segmentation Data Fetch Control; TCP Segmentation Performance
  • Page 149 – Packet Format; TCP Segmentation Indication
  • Page 151 – IP and TCP/UDP Headers
  • Page 157 – TCP/IP/UDP Header for the Subsequent Frames
  • Page 158 – Offloading
  • Page 159 – Offloading in Non-Segmentation Mode; IP Checksum
  • Page 160 – TCP Checksum
  • Page 161 – Tx Completions Head Write-Back
  • Page 162 – Interrupts
  • Page 163 – Interrupt Acknowledge Auto-mask register
  • Page 164 – Extended Interrupt Cause Set Register (EICS)
  • Page 165 – Interrupt Modes Setting Bits; Interrupt Moderation
  • Page 168 – Clearing Interrupt Causes
  • Page 169 – Write to Clear; Dynamic Interrupt Moderation
  • Page 170 – TCP Timer Interrupt; Memory Error Correction and Detection
  • Page 171 – General Functionality
  • Page 172 – Data Alignment; KB Boundary; Transaction Attributes; Traffic Class and Virtual Channels
  • Page 173 – Relaxed Ordering; No Snoop and Relaxed Ordering for LAN Traffic; No Snoop Option for Payload
  • Page 174 – Flow Control; Flow Control Rules; Upstream Flow Control Tracking
  • Page 175 – Flow Control Update Frequency; Host Interface; Tag IDs
  • Page 179 – Completion Timeout Mechanism
  • Page 180 – Error Events and Error Reporting; Error Events
  • Page 182 – Error Pollution
  • Page 183 – Link Layer; Supported DLLPs
  • Page 184 – Transmit EDB Nullifying; Physical Layer; Link Width
  • Page 185 – Polarity Inversion
  • Page 186 – Reset; Performance Monitoring; PCI Compatibility
  • Page 187 – Mandatory PCI Configuration Registers
  • Page 193 – PCI Power Management Registers
  • Page 195 – Message Signaled Interrupt (MSI) Configuration
  • Page 199 – PCIe* Configuration Registers
  • Page 208 – PCIe* Extended Configuration Space
  • Page 209 – Advanced Error Reporting Capability
  • Page 213 – Power States
  • Page 214 – Auxiliary Power; Form Factor Power Limits
  • Page 215 – Power Management Interconnects; PCIe* Link Power Management
  • Page 217 – PHY Power Management; Link Speed Control
  • Page 218 – D0a State
  • Page 219 – Link Energy Detect
  • Page 220 – Dr State; Dr Disable Mode
  • Page 221 – Entry to Dr State; D0 Uninitialized State; Entry to D0u State
  • Page 222 – D0 Active State; Entry to D0a State; D3 State; Entry to D3 State
  • Page 223 – Master Disable
  • Page 224 – Power-State Transitions Timing
  • Page 225 – Transition from D0a to D3 and Back without PE_RST_N
  • Page 226 – Transition from D0a to D3 and Back with PE_RST_N
  • Page 227 – D0a to Dr and Back without Transition to D3
  • Page 228 – Timing Guarantees
  • Page 229 – Wake Up; Advanced Power Management Wakeup
  • Page 230 – PCIe Power Management Wakeup
  • Page 231 – Directed Exact Packet
  • Page 232 – Broadcast
  • Page 233 – ARP/IPv4 Request Packet
  • Page 234 – Directed IPv6 Packet; Flexible Filter
  • Page 235 – IPX Diagnostic Responder Request Packet
  • Page 236 – IPv6 Neighbor Discovery Filter; Wake Up Packet Storage
  • Page 237 – DCA; Implementation Details
  • Page 240 – Interface
  • Page 241 – Duplex Operation for Copper PHY; Full Duplex
  • Page 242 – Half Duplex; B10B Encoding/Decoding
  • Page 243 – Code Groups and Ordered Sets
  • Page 244 – Auto-Negotiation and Link Setup; SerDes Link Configuration; SerDes Mode Auto-Negotiation
  • Page 245 – PCS Hardware Auto-Negotiation; Forcing Link
  • Page 246 – Hardware Detection of Non-Auto-Negotiation Partner
  • Page 247 – Copper PHY Link Configuration; MAC Speed Resolution; Forcing MAC Speed
  • Page 248 – Using Internal PHY Direct Link-Speed Indication; MAC Full/Half Duplex Resolution
  • Page 249 – Comments Regarding Forcing Link; Loss of Signal/Link Status Indication
  • Page 250 – MAC Control Frames and Reception of Flow Control
  • Page 252 – Discard PAUSE Frames and Pass MAC Control; Transmission of PAUSE Frames
  • Page 253 – Software Initiated PAUSE Frame Transmission; Loopback Support
  • Page 254 – MAC Loopback; Setting the 82575 to MAC Loopback Mode; Internal PHY Loopback; Setting the 82575 to Internal PHY Loopback Mode
  • Page 255 – Internal SerDes Loopback; Setting Internal SerDes Loopback Mode; External PHY Loopback
  • Page 256 – Setting External PHY Loopback Mode
  • Page 258 – Transmitting and Receiving 802.1q; Adding 802.1q Tags on Transmits
  • Page 259 – Stripping 802.1q Tags on Receives; q VLAN Packet Filtering
  • Page 260 – Double VLAN Support
  • Page 261 – PHY Functionality and Features; Auto MDIO Register Initialization; General Register Initialization
  • Page 262 – Determining Link State; False Link
  • Page 263 – Forced Operation; Auto Negotiation
  • Page 264 – Parallel Detection; Support for Different Board Layouts
  • Page 265 – Link Criteria; SmartSpeed
  • Page 266 – Using SmartSpeed
  • Page 267 – Management Data Interface
  • Page 268 – Transmit Functions; Scrambler
  • Page 269 – Transmit FIFO; Transmit Phase-Locked Loop PLL; Spectral Shaper
  • Page 270 – Line Driver
  • Page 271 – Receive Functions; Hybrid
  • Page 272 – DPAM5 Decoder; Link Test
  • Page 273 – 0Base-T Link Failure Criteria and Override
  • Page 275 – Configurable LED Outputs
  • Page 277 – Dual Port Characteristics; Features of Each MAC
  • Page 279 – MAC Configuration Register Space; FLASH Access Contention
  • Page 280 – Link Mode/Configuration; Overview
  • Page 281 – Multi-Function Advertisement; Legacy Interrupt Use; Power Reporting; Device Disable
  • Page 282 – BIOS Handling of Device Disable
  • Page 287 – Register Descriptions; Register Conventions
  • Page 289 – Memory and I/O Address Decoding; Memory-Mapped Access to Internal Registers and
  • Page 290 – Memory-Mapped Access to Expansion ROM; IOADDR
  • Page 291 – IODATA
  • Page 292 – Undefined I/O Offsets; Register Summary
  • Page 298 – Main Register Descriptions
  • Page 306 – Extended Device Control Register - CTRL_EXT
  • Page 311 – PHY Registers
  • Page 316 – Auto-Negotiation Next Page Transmit Register - NPT
  • Page 317 – Auto-Negotiation Next Page Ability Register - LPN
  • Page 329 – Flow Control Transmit Timer Value - FCTTV
  • Page 330 – MODE Encodings for LED Outputs
  • Page 335 – Manageability EEPROM Control Register -
  • Page 336 – Manageability Flash Control Register -
  • Page 337 – Manageability Flash Read Counter - FLMNGCNT
  • Page 338 – Watchdog SW Device Status - WDSWSTS
  • Page 344 – Interrupt Acknowledge Auto Mask Register -
  • Page 347 – Extended Interrupt Auto Mask Enable - EIAM
  • Page 350 – Immediate Interrupt Rx Extended - IMIREXT
  • Page 354 – Split and Replication Receive Control - SRRCTL
  • Page 356 – Flow Control Receive Threshold Low - FCRTL
  • Page 357 – Flow Control Receive Threshold High - FCRTH; Flow Control Refresh Threshold Value - FCRTV
  • Page 358 – Receive Descriptor Base Address Low - RDBAL; Receive Descriptor Base Address High - RDBAH
  • Page 362 – Receive Long Packet Maximum Length - RLPML
  • Page 366 – Transmit Descriptor Base Address Low - TDBAL
  • Page 368 – Transmit Descriptor Control - TXDCTL (03828h
  • Page 369 – Tx Descriptor Completion Write-Back Address
  • Page 376 – Link Partner Ability Next Page - PCS_LPABNP; DCA Registers
  • Page 378 – Filter Registers
  • Page 379 – Multicast Table Arra
  • Page 382 – Multiple Receive Queues Command Register -
  • Page 385 – Wakeup Registers
  • Page 386 – Wakeup Filter Control Register - WUFC
  • Page 391 – Manageability Registers; Management VLAN TAG Value - MAVTV (5010h
  • Page 394 – Management Control to Host Register - MANC2H
  • Page 395 – Manageability IP Address Filter - MIPAF
  • Page 398 – Manageability MAC Address Low - MMAL (5910h; Manageability MAC Address High - MMAH; Flexible TCO Filter Table Registers - FTFT
  • Page 408 – Function Active and Power State to MNG -
  • Page 413 – Using the Software-Firmware Synchronization
  • Page 416 – Statistics Registers
  • Page 420 – FC Received Unsupported Count - FCRUC
  • Page 423 – Broadcast Packets Received Count - BPRC
  • Page 424 – Good Octets Transmitted Count - GOTCL
  • Page 426 – Management Packets Received Count - MNGPRC
  • Page 429 – Packets Transmitted (1024 Bytes or Greater)
  • Page 430 – Multicast Packets Transmitted Count - MPTC
  • Page 431 – Receive Descriptor Minimum Threshold Count -
  • Page 432 – SerDes/SGMII Code Violation Packet Count -; Diagnostics Registers; Receive Data FIFO Head Register - RDFH
  • Page 433 – Receive Data FIFO Head Saved Register -
  • Page 434 – PB Descriptor Read Pointers - PBDESCRP
  • Page 435 – Transmit Data FIFO Tail Register - TDFT
  • Page 436 – Transmit Data FIFO Packet Count - TDFPC
  • Page 437 – Tx Descriptor Handler ECC Error Inject - TDHEEI
  • Page 438 – Packet Buffer Memory Page NPBMPN Register
  • Page 439 – Tx Descriptor Handler Memory Page Number -
  • Page 440 – Rx Descriptor Handler ECC Status - RDHESTS
  • Page 441 – Tx Descriptor Handler ECC Status - TDHESTS; Packet Generator Registers; Packet Generator Destination Address Low -
  • Page 442 – Packet Generator Source Address Low - PGSAL
  • Page 443 – Packet Generator Packet Length - PGPL
  • Page 444 – Packet Generator StaPGSTS Bit Description
  • Page 446 – MSI-X Table Entry Lower Address - MSIXTADD
  • Page 449 – Diagnostics and Testability; Diagnostics; FIFO Pointer Accessibility
  • Page 450 – Testability; EXTEST Instruction
  • Page 451 – BYPASS Instruction
  • Page 455 – RMON
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324632-003

Revision: 2.1

January 2011

Intel

®

82575EB Gigabit Ethernet

Controller Software Developer’s

Manual and EEPROM Guide

LAN Access Division

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Summary

Page 2 - Legal

Intel ® 82575EB Gigabit Ethernet Controller — Legal Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 2 January 2011 Legal INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY E...

Page 3 - Revisions

Revisions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 3 Revisions Revision Date Description .25 2/2006 Initial release (Intel Secret). 1.1 1/2008 • Updated Section 13.4.8....

Page 4 - Content

Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 4 January 2011 Content 1.0 Introduction ...............................................................................................

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