Page 2 - ii; Datasheet
82555 — Networking Silicon ii Datasheet Revision History ■ Low power consumption — Typical total solution power including all resistors and magnetics: - 275 mA 100BASE-TX - 230 mA 10BASE-T - 250 mA Auto-Negotiation — 300 mA maximum total solution power in DTE (adapter) mode — Power-down of 10BASE-T/...
Page 3 - iii; Contents
Datasheet iii Networking Silicon — 82555 Contents 1.0 INTRODUCTION .......................................................................................................................... 1 1.1 Functional Overview .......................................................................................
Page 4 - iv
82555 — Networking Silicon iv Datasheet Contents 5.3.3 10BASE-T Error Detection and Reporting ................................................. 22 5.4 10BASE-T Collision Detection....................................................................................... 22 5.5 10BASE-T Link Integrity .....
Page 5 - Introduction; Functional Overview; a repeater type of application.; Compliance to Industry Standards
Datasheet 1 Networking Silicon — 82555 1.0 Introduction The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over tw...
Page 7 - Architectural Overview; Figure 2
Datasheet 3 Networking Silicon — 82555 2.0 Architectural Overview The 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 shows a general block diagram...
Page 8 - MII TX Interface; Magnetics Module
82555 — Networking Silicon 4 Datasheet • Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and converts it into a digital 125 Mbps stream, recovering both clock and data signals. 2.2 10 Mbps Mode The 82555 operation in 10BASE-T mode is similar to the 82555 operati...
Page 9 - Figure 4; PCI Bus Signals
Datasheet 5 Networking Silicon — 82555 The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the 82557 Fast Ethernet controller implementation connected to the 82555 us...
Page 11 - Pin Definitions
Datasheet 7 Networking Silicon — 82555 3.0 Pin Definitions All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively....
Page 12 - Pin Types
82555 — Networking Silicon 8 Datasheet Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board layout and other design constraints. 3.1 Pin Types 3.2 Clock Pins 3.3 Twisted Pair Ethernet (TPE) Pins 3.4 Media Independent Interface (MII) Pins Pin T...
Page 13 - Media Access Control/Repeater Interface Control Pins
Datasheet 9 Networking Silicon — 82555 3.5 Media Access Control/Repeater Interface Control Pins RXC 90 O Receive Clock. The Receive Clock may be either 25 MHz or 2.5 MHz depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps). The Receive Clock is recovered directly fr...
Page 14 - LED Pins
82555 — Networking Silicon 10 Datasheet 3.6 LED Pins 3.7 External Bias Pins Note: The resistor values described for the external bias pins are only recommended values and may require to be fine tuned for various designs. TXRDY (TOUT) 4 O This pin is multiplexed and can be used for one of the followi...
Page 15 - Miscellaneous Control Pins
Datasheet 11 Networking Silicon — 82555 3.8 Miscellaneous Control Pins Symbol Pin Type Name and Function RESET 1 I Reset. The Reset signal is active high and resets the 82555. A reset pulse width of at least 1 µ s should be used. FRC100 (MACTYP) 51 I This pin is multiplexed and can be used for one o...
Page 16 - Power and Ground Pins
82555 — Networking Silicon 12 Datasheet 3.9 Power and Ground Pins Symbol Pin Type Name and Function VCC 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62, 64, 66, 73, 75, 83, 88, 93, 98 I Power: +5 V ± 5% VSS 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39, 41, 46, 49, 53, 57, 61, 63, 65, 67...
Page 17 - 00BASE-TX Adapter Mode Operation; 00BASE-TX Transmit Clock Generation
Datasheet 13 Networking Silicon — 82555 4.0 100BASE-TX Adapter Mode Operation 4.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. Th...
Page 19 - 00BASE-TX Transmit Framing
Datasheet 15 Networking Silicon — 82555 maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to the next level. The order of steps is negative-zero-positive-zero which continues periodically. The figure below illustrates this process. ...
Page 20 - Transmit Driver; The magnetics module that is external to the 82555 converts I; and I; 00BASE-TX Receive Blocks; Figure 7. Conceptual Transmit Differential Waveform; Table 3. Magnetics Modules
82555 — Networking Silicon 16 Datasheet 4.2.4 Transmit Driver The transmit differential lines are implemented with a digital slope controlled current driver that meets the TP-PMD specifications. Current is sunk from the isolation transformer by the transmit differential pins. The conceptual transmit...
Page 21 - Adaptive Equalizer; Link integrity fails in the middle of frame reception.; 00BASE-TX Collision Detection
Datasheet 17 Networking Silicon — 82555 4.3.1 Adaptive Equalizer The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior Data Dependent Jitter performance. 4.3....
Page 22 - 00BASE-TX Link Integrity and Auto-Negotiation Solution; Link Integrity
82555 — Networking Silicon 18 Datasheet 4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution The 82555’s Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE specificati...
Page 23 - Adapter Mode Addresses; Figure 8. Combination Card Example
Datasheet 19 Networking Silicon — 82555 The figure below illustrates an 82557/82555/PHY-T4 solution in a block diagram. 4.6 Auto 10/100 Mbps Speed Selection The MAC may either allow the 82555 to automatically select its operating speed or force the 82555 into 10 Mbps or 100 Mbps mode. The Management...
Page 25 - 0BASE-T Functionality in Adapter Mode; 0BASE-T Transmit Clock Generation; 0BASE-T Manchester Encoder; 0BASE-T Receive Blocks; 0BASE-T Manchester Decoder
Datasheet 21 Networking Silicon — 82555 5.0 10BASE-T Functionality in Adapter Mode 5.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MA...
Page 26 - Differential pulses of peak magnitude less than 300 mV.; and frequency less than 2; and a frequency of at least 2 MHz and not more than 16 MHz.; 0BASE-T Error Detection and Reporting; 0BASE-T Collision Detection
82555 — Networking Silicon 22 Datasheet Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard. The following line activ...
Page 29 - Repeater Mode; Special Repeater Features; Special features of the 82555 repeater mode operation include:; Connectivity
Datasheet 25 Networking Silicon — 82555 6.0 Repeater Mode The 82555 has a compete set of repeater features making it the ideal PHY for Class 1 (MII) repeater designs. The 82555 works in repeater mode when the RPT signal (pin 50) is high. The FRC100 signal (pin 51) determines which type of repeater i...
Page 31 - Management Data Interface; MDI Frame Structure
Datasheet 27 Networking Silicon — 82555 7.0 Management Data Interface The 82555 provides status and accepts management information through the Management Data Interface (MDI). This is accomplished through read and write operations to various registers in accordance with the IEEE 802.3u MII specifica...
Page 32 - MDI Registers; P- External pin affects 82555 register content.; Register 0: Control Register Bit Definitions
82555 — Networking Silicon 28 Datasheet The 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode. The management frame structure is as follows: 7.2 MDI Registers MDI...
Page 33 - Register 1: Status Register Bit Definitions
Datasheet 29 Networking Silicon — 82555 7.2.1.2 Register 1: Status Register Bit Definitions 11 Power-Down This bit sets the 82555 into a low power mode. 1 = Power-down enabled 0 = Power-down disabled (normal operation) 0 RW 10 Isolate This bit allows the 82555 to electrically isolate the Media Indep...
Page 34 - Register 2: 82555 Identifier Register Bit Definitions
82555 — Networking Silicon 30 Datasheet 7.2.1.3 Register 2: 82555 Identifier Register Bit Definitions 7.2.1.4 Register 3: 82555 Identifier Register Bit Definitions 7.2.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions 6 Management Frames Preamble Suppression 1 = 82555 will acce...
Page 35 - Register 6: Auto-Negotiation Expansion Register Bit Definitions; Registers eight through fifteen are reserved for IEEE.
Datasheet 31 Networking Silicon — 82555 7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions 7.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions 7.2.2 MDI Registers 8 - 15 Registers eight through fifteen are reserved for IEEE. 7.2.3 MDI Registers 16 ...
Page 36 - Register 16: 82555 Status and Control Register Bit Definitions
82555 — Networking Silicon 32 Datasheet 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions 7.2.3.2 Register 17: 82555 Special Control Bit Definitions Bit(s) Name Description Default R/W 15 Flow Control This bit enables PHY Base (Bay Technologies) flow control. 1 = Enable PHY Base...
Page 38 - Register 22: Receive Symbol Error Counter Bit Definitions
82555 — Networking Silicon 34 Datasheet 7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions 7.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions 7.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions 7.2.3.8 Register 25:...
Page 39 - Auto-Negotiation Functionality; Description; Table 4; Table 4. Technology Ability Field Bit Assignments; Table 5. Technology Priority
Datasheet 35 Networking Silicon — 82555 8.0 Auto-Negotiation Functionality The 82555 supports Auto-Negotiation. Auto-Negotiation is a scheme of auto-configuration designed to manage interoperability in multifunctional LAN environments. It allows two stations with “N” different modes of communication...
Page 40 - The following is an outline of the Auto-Negotiation process:; Parallel Detect and Auto-Negotiation
82555 — Networking Silicon 36 Datasheet To detect the correct technology, the two register fields should be ANDed together to obtain the highest common denominator. This value should then be used to map into a priority resolution table used by the MAC driver to use the appropriate technology. The fo...
Page 43 - LED Descriptions; MDI register 27 in
Datasheet 39 Networking Silicon — 82555 9.0 LED Descriptions The 82555 supports four LED pins to indicate link status, network activity and network speed. • Link: This LED is off (logic high) until a valid link has been detected. After a valid link has been detected, the LED will remain on (active-l...
Page 45 - Reset and Miscellaneous Test Modes; Reset
Datasheet 41 Networking Silicon — 82555 10.0 Reset and Miscellaneous Test Modes 10.1 Reset When the 82555 RESET signal is asserted (high), all internal circuits are reset. TXC and RXC should run continuously even though RESET is active. The 82555 may also be reset through the MDI reset bit. 10.2 Loo...
Page 47 - Electrical Specifications and Timing Parameters; Absolute Maximum Ratings; MII DC Characteristics
Datasheet 43 Networking Silicon — 82555 11.0 Electrical Specifications and Timing Parameters 11.1 Absolute Maximum Ratings 11.2 General Operating Conditions 11.3 DC Characteristics 11.3.1 MII DC Characteristics 11.3.2 10BASE-T Voltage/Current DC Characteristics Symbol Parameter Description Min Typ M...
Page 48 - 00BASE-TX Voltage/Current DC Characteristics; Figure 11. RBIAS10 Resistance versus I
82555 — Networking Silicon 44 Datasheet 11.3.3 100BASE-TX Voltage/Current DC Characteristics V IDA10 Input differential accept voltage 5 MHz ≤ f ≤ 10 MHz ±585 ±3100 mV P V IDR10 Input differential reject voltage 5 MHz ≤ f ≤ 10 MHz ±300 mV P V ICM10 Input common mode voltage V CC /2 V V OD10 Output d...
Page 49 - AC Characteristics; MII Clock Specifications; Figure 12. RBIAS100 Resistance versus I; Output Levels
Datasheet 45 Networking Silicon — 82555 11.4 AC Characteristics 11.4.1 MII Clock Specifications I CC100 c Current on all V CC pins 235 mA I CCT100TOT Total supply current 275 mA a. Transmitter current is measured with a 1:1 transformer on the center tap.b. Transmitter current is measured with a 1:1 ...
Page 50 - MII Timing Parameters; Figure 14. MII Clocks AC Timing
82555 — Networking Silicon 46 Datasheet 11.4.2 MII Timing Parameters Figure 14. MII Clocks AC Timing T 1 , T 2 , T 3 1 . 5 V T 4 , T 5 , T 6 T 4 , T 5 , T 6 Symbol Parameter Conditions Min Typ Max Units T7 T TXDV TXD[3:0], TXEN, TXERR setup from the rising edge of TXC 15 25 ns T8 T TXH TXD[3:0], TXE...
Page 51 - Repeater Mode Timing Parameters; Figure 16. MII Receive Timing Parameters; Figure 18. PORT Enable Timing
Datasheet 47 Networking Silicon — 82555 11.4.3 Repeater Mode Timing Parameters Figure 16. MII Receive Timing Parameters Figure 17. MII Timing Parameters: MDC/MDIO T 9 T 1 0 R X C L K R X D [ 3 : 0 ] , R X E R , R X D V D a t a I n v a l i d D a t a I n v a l i d D a t a V a l i d T 1 1 T 1 2 M D C M...
Page 52 - Transmit Packet Timing Parameters; Figure 19. Transmit Frame Timing Parameters
82555 — Networking Silicon 48 Datasheet 11.4.4 Transmit Packet Timing Parameters 11.4.5 Squelch Test Timing Parameters Symbol Parameter Conditions Min Typ Max Units T15 T XEN_ST TXC on first TXEN active to start of frame 100 Mbps 10 12 bits T15a T XEN_ST TXC on first TXEN active to start of frame 10...
Page 53 - Jabber Timing Parameters; Figure 20. Squelch Test Timing Parameters; Figure 21. Jabber Timing Parameters
Datasheet 49 Networking Silicon — 82555 11.4.6 Jabber Timing Parameters 11.4.7 Receive Packet Timing Parameters Figure 20. Squelch Test Timing Parameters T X E N C O L T X C L K T 2 0 T 2 1 Symbol Parameter Conditions Min Typ Max Units T22 T JAB_ON Jabber turn-on delay (TXEN asserted to end of trans...
Page 54 - Figure 23. Normal Link Pulse Timing Parameters
82555 — Networking Silicon 50 Datasheet 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters T26a T R_CRSL End of receive frame to falling edge of CRS 10 Mbps 4.5 bits T27 T R_RXDVL End of receive frame to falling edge of RXDV 100 ...
Page 55 - Reset Timing Parameters; Figure 24. Fast Link Pulse Timing Parameters; Figure 25. Reset Timing Parameters
Datasheet 51 Networking Silicon — 82555 11.4.10 Reset Timing Parameters 11.4.11 X1 Clock Specifications T33 T FLP_BUR_NUM Number of pulses in one burst 17 33 T34 T FLP_BUR_WID FLP Burst width 2 ms T35 T FLP_BUR_PER FLP burst period 8 24 ms Symbol Parameter Conditions Min Typ Max Units Figure 24. Fas...
Page 56 - 00BASE-TX Transmitter AC Specification; Figure 26. X1 Clock Specifications
82555 — Networking Silicon 52 Datasheet 11.4.12 100BASE-TX Transmitter AC Specification Figure 26. X1 Clock Specifications T 3 8 2 . 5 V T 3 9 T 3 9 0 . 4 V 4 . 0 V Symbol Parameter Conditions Min Typ Max Units T40 T JIT TDP/TDN differential output peak jitter HLS data 300 700 ps
Page 57 - Table 7
Datasheet 53 Networking Silicon — 82555 12.0 82555 Package Information This section provides the physical packaging information for the 82555. The 82555 is an 100-pin plastic Quad Flat Pack (QFP) device. Package attributes are provided in Table 7 and the dimensions are shown in Figure 27 . Figure 27...
