Intel IQ80321 - Manual

Intel IQ80321

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Table of Contents:

  • Page 2 – Intel
  • Page 3 – Contents
  • Page 8 – Figures
  • Page 9 – Tables
  • Page 11 – Revision History
  • Page 12 – This page intentionally left blank.
  • Page 13 – Introduction; Document Purpose and Scope; This document describes the Intel; Related Documents; To obtain Intel literature write to or call:
  • Page 14 – Table 3; Electronic Information; Component Reference
  • Page 15 – Terms and Definitions
  • Page 18 – Summary of Features
  • Page 19 – Getting Started; Kit Content; First-Time Installation and Test
  • Page 20 – Factory Settings; “Switches and Jumpers” on page 52; Development Strategy; Supported Tool Buckets; LynuxWorks* Embedded Linux RTOS and Development Tools; Contents of the Flash
  • Page 21 – Target Monitors; Redhat Redboot; Here are some highlights of RedBoot capabilities:
  • Page 22 – ARM Firmware Suite
  • Page 23 – ARM Angel; CPU and board startup and basic exception handling
  • Page 24 – Host Communications Examples; How to communicate to the host.; Using a serial connection:; Ethernet-Network Communication; Serial-UART Communication; Ethernet-Network Communication
  • Page 25 – Using a JTAG Emulator:; JTAG Debug Communication
  • Page 26 – Communicating with Redboot
  • Page 28 – Connecting with GDB
  • Page 29 – ARM Extended Debugger; From CodeWarrior open project and start debugger:
  • Page 31 – Hardware Reference Section; Functional Diagram; Figure 5; Functional Block Diagram; Bridge
  • Page 32 – Board Form Factor
  • Page 33 – Power; Table 7; Power Features
  • Page 34 – Memory Subsystem; DDR SDRAM; Battery Backup; DDR Memory Features; Supported DIMM Types
  • Page 35 – Total Flash memory size is 8 MB.; Flash Memory Requirements
  • Page 37 – Interrupt Routing; External Interrupt Routing to Intel
  • Page 38 – The IQ80321 populates the peripheral bus as depicted by; Peripheral Bus Features
  • Page 39 – Flash ROM; Flash ROM Features; Flash Connection on Peripheral Bus
  • Page 40 – UART; UART Features; UART Connection on the Peripheral Bus
  • Page 41 – HEX Display; HEX Display on the Peripheral Bus; HEX Display Connection on the Peripheral Bus
  • Page 42 – Rotary Switch; Rotary Switch Requirements; Rotary Switch Connection on the Peripheral Bus
  • Page 43 – Battery Status Buffer Requirements; Battery Status Buffer on Peripheral Bus
  • Page 44 – Debug Interface; Console Serial Port; Evaluation Platform Board Peripheral Bus” on page 38; Ethernet Port; 2544EI Gigabit Ethernet Controller on the secondary PCI-X bus.
  • Page 45 – JTAG Debug; JTAG Port; Logic-Analyzer Connectors; to a NC pin, hardware damage can be incurred.; Logic Analyzer Connection
  • Page 46 – Micor J3F2 Signal/Pins
  • Page 47 – Micor J2F1 Signal/Pins
  • Page 48 – Micor J1C1 Signal/Pins
  • Page 49 – Micor J3C1 Signal/Pins
  • Page 50 – Micor J2C1 Signal/Pins
  • Page 51 – Board Reset Scheme; depicts the reset scheme for the IQ80321.; Reset Requirements/Schemes; RESET Sources
  • Page 52 – Switches and Jumpers; Switch Summary
  • Page 53 – PCIX Initialization Summary; secondary side of the PCI-X bridge. The Intel; User Defined Switches; User can set the PCIXCAP signal to force one of the following modes:; PCI-X Bridge Initialization Signals; PCI-X Routing Diagram on Secondary PCI-X Bridge; PCI
  • Page 54 – Default Switch Settings - Visual
  • Page 55 – Jumper Summary
  • Page 57 – Detail Descriptions of Switches/Jumpers; Operation Setting Summary Descriptions
  • Page 58 – Switch S7E1 - 4: Settings and Operation Mode
  • Page 59 – Switch S7E1 - 8: Settings and Operation Mode
  • Page 60 – Switch S8E1 - 2: Settings and Operation Mode
  • Page 61 – Switch S8E1 - 5: Settings and Operation Mode
  • Page 62 – Switch S8E1 - 7: Settings and Operation Mode
  • Page 63 – Switch S8E2 - 4: Settings and Operation Mode
  • Page 64 – Switch S9E1 - 4: Settings and Operation Mode
  • Page 67 – Jumper J9E1: Descriptions
  • Page 69 – External RAID Section; Private Device Configuration; The devices on the SPCI-X bus (Expansion Slot and Intel; Private Device Configuration Requirements; IDSEL Routing for Private Device Configuration
  • Page 70 – Controllerr) are routed based on requirements.; Interrupt Routing for Secondary PCI-X Private Device; Interrupt Routing for Private Device Configuration
  • Page 71 – Software Reference; DRAM; Processor Developer ’s Manual.; Components on the Peripheral Bus; DDR Memory Bias Voltage Minimum/Maximum Values
  • Page 72 – The Flash ROM is an 8 MB Intel; Flash Connection to Peripheral Bus
  • Page 73 – UART Connection to Peripheral Bus
  • Page 74 – Hex Display Connection to Peripheral Bus
  • Page 76 – Ethernet; For more detail see
  • Page 77 – depicts the memory space for the IQ80321 (before Redboot boots):
  • Page 79 – Redboot Intel
  • Page 81 – Attached in the kit, find a copy of the Red Hat eCos for Intel
  • Page 82 – Initialization Sequence:
  • Page 83 – Redboot Switching; All other switches are left in default positions.
  • Page 85 – 0310 I/O Processor Chipset to the Intel
  • Page 87 – Getting Started and Debugger; Appendix C, “Getting Started and; Purpose; Code|Lab EDE debugger
  • Page 88 – Related Web Sites
  • Page 89 – Setup; Hardware Setup; Use
  • Page 90 – Software Setup; Software Flow Diagram
  • Page 91 – New Project Setup; Creating a New Project; a. Fill-in the Project Name box with “Tester321LED”; b. Select the appropriate evaluation board.
  • Page 92 – Configuration; There is no main menu way to access the project settings.
  • Page 93 – Flashing with JTAG; Overview
  • Page 94 – Using Flash Programmer
  • Page 95 – Debugging Out of Flash; Launch Code|Lab EDE and open the “Tester321LED” Workspace.
  • Page 96 – Running the Code|Lab Debugger; Launching and Configuring Debugger
  • Page 97 – Manually Loading and Executing an Application Program; Launch the Code|Lab Debug Environment from the desktop icon.; Displaying Source Code; Use the File/Recent Programs menu for quick access.
  • Page 98 – Using Breakpoints
  • Page 99 – Stepping Through the Code
  • Page 100 – Exploring the Code|Lab Debug Windows; Toolbar Icons; 0321 I/O Processor Developer ’s
  • Page 101 – Registers Window; Click the “Watch” icon to bring up the Watch window.; Variables Window
  • Page 102 – Debugging Basics; Developer’s Manual, for more detailed information.; Software Breakpoints; of this Guide. Program execution can be halted at a; Hardware Breakpoints
  • Page 113 – When there are errors, carefully go back through
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Intel

®

IQ80321 I/O Processor

Evaluation Platform

Board Manual

April 2, 2003

Document Number:

273521-008

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Summary

Page 2 - Intel

2 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS...

Page 3 - Contents

Board Manual 3 Intel ® IQ80321 I/O Processor Evaluation Platform Contents Contents 1 Introduction .................................................................................................................................. 13 1.1 Document Purpose and Scope ........................................

Page 8 - Figures

8 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Contents Figures 1 Intel ® 80321 I/O Processor Block Diagram ................................................................................ 16 2 Serial-UART Communication .................................................................

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