Intel 820E - Manual

Intel 820E

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Table of Contents:

  • Page 3 – Contents; Intel
  • Page 4 – System Bus Design – Pentium
  • Page 6 – Clock Routing Guidelines for Intel
  • Page 8 – Figures
  • Page 9 – 20E Chipset Clock Routing Guidelines
  • Page 10 – Tables
  • Page 12 – Revision History
  • Page 13 – About This Design Guide
  • Page 14 – Documents
  • Page 15 – Overview; III
  • Page 16 – Components; Chapter 2 Layout/Routing Guidelines
  • Page 17 – FWH Flash BIOS; Summary; 20E Chipset Platform Bandwidth Summary
  • Page 18 – Configuration; 20E Chipset Platform Performance Desktop Block Diagram
  • Page 20 – Initiatives; Streaming SIMD Extensions; for photorealistic 3D. In; Interface
  • Page 21 – Integrated LAN Controller; The Intel; Ultra ATA/100 Support; TCO Timer
  • Page 22 – Function Disable
  • Page 27 – Guidelines; Recommendations
  • Page 28 – GP; ub i
  • Page 29 – 20E Chipset Component Placement; Figure 7. Sample ATX and NLX MCH/ICH2 Component Placement; Actual ICH2 placement may vary.
  • Page 30 – Core Chipset Routing Recommendations; The following two figures show MCH core routing examples:
  • Page 32 – Strobing; A technology used in AGP 4; Figure 10. Data Strobing Example; Clock; very important; that the strobe signals be routed; Figure 11. Effect of Crosstalk on Strobe Signal; ) are listed in the following
  • Page 33 – timings; Direct RDRAM* Interface; Figure 12. RIMM Diagram
  • Page 34 – Direct RDRAM* Layout Guidelines; RSL signals
  • Page 35 – Routing; Figure 13. RSL Routing Dimensions; To maintain a nominal 28; Table 3. Placement Guidelines for Motherboard Routing Lengths
  • Page 36 – Figure 14. RSL Routing Diagram; Figure 15. Primary-Side RSL Breakout Example
  • Page 37 – Figure 16. Secondary-Side RSL Breakout Example
  • Page 38 – Termination; at least
  • Page 39 – Figure 18. Direct RDRAM* Termination Example; Direct RDRAM* Ground Plane Reference; capacitors. The ground reference; capacitors into the ground island and under the RSL; island to be on an outer layer. The V; island should; always; be placed on the
  • Page 40 – Figure 19. Incorrect Direct RDRAM* Ground Plane Referencing; Wrong; Figure 20. Direct RDRAM* Ground Plane Reference; GND Plane; Required
  • Page 41 – Direct RDRAM* Connector Compensation; Equation 1. Approximate Copper Tab Area Calculation
  • Page 42 – Table 4. Copper Tab Area Calculation
  • Page 43 – Figure 21. Connector Compensation Example
  • Page 47 – Recommendation
  • Page 48 – Table 6. Copper Tab Area Calculation; Figure 26. Top-Layer CTAB with RSL Signal Routed on the Same Layer (C
  • Page 49 – RSL Signal Layer Alternation
  • Page 50 – Figure 29. RSL Signal Layer Alternation; Table 7. RSL Routing Layer Requirements; Length Matching Methods; Given the following definitions:; exactly
  • Page 51 – Equation 2. RDRAM RSL Signal Trace Length Calculation; Refer to the; Equation 3. RDRAM Clock Signal Trace Length Calculation; only
  • Page 52 – Compensation; Real via = Dummy via + 25 mils of trace length; “REAL Via”; PCB; Length Matching and Via Compensation Example; 000 mils was chosen as an
  • Page 53 – Table 8. Line Matching and Via Compensation Example
  • Page 54 – Direct RDRAM* Reference Voltage; each; RIMM connector, at the resistor divider, and at the; Figure 32. RAMREF Generation Example Circuit; High-Speed CMOS Routing; The resistors must be 91
  • Page 55 – Figure 34. SIO Routing Example
  • Page 56 – of 4 pF or less; Figure 35. RDRAM CMOS Shunt Transistor; CMD
  • Page 57 – Direct RDRAM* Clock Routing; Chapter 4 Clocking; Direct RDRAM* Design Checklist; Table 9. Signal List; not
  • Page 58 – very
  • Page 59 – entirely; must; Section
  • Page 60 – AGP Interface Signal Groups
  • Page 61 – Signal Groups
  • Page 62 – × Timing Domain Routing Guidelines; ×/4× Timing Domain Routing Guidelines; all; Interfaces < 6 Inches
  • Page 63 – Figure 36. AGP 2×/4× Routing Example for Interfaces < 6 Inches
  • Page 64 – All AGP Interfaces; When matching the trace length for the AGP 4; not be violated by any signal. Trace length; AGP 2.0 Routing Summary
  • Page 65 – AGP Clock Routing; General AGP Routing Guidelines; Decoupling; For V; F capacitors are required, of which at least four must be
  • Page 66 – Figure 37. Top Signal Layer; Ground Reference; Generation and TYPEDET#
  • Page 67 – Relationship; the AGP 2.0 Interface Specification
  • Page 68 – Generation Example Circuit
  • Page 69 – Generation and Distribution
  • Page 71 – AGP Signal Voltage Tolerance List; Motherboard / Add-in Card Interoperability; Table 14. Voltage / Data Rate Interoperability
  • Page 72 – Figure 40. AGP Left-Handed Retention Mechanism
  • Page 74 – . Layer transition should be keep to a minimum. If a layer; Figure 42. Hub Interface Signal Routing Example
  • Page 75 – -Bit Hub Interface Routing Guidelines; enhanced buffer mode, the trace impedance can be 50; Table 15. 8-Bit Hub Interface Buffer Configuration Setting; -Bit Hub Interface Data Signals
  • Page 76 – HUBREF
  • Page 77 – -Bit Hub Interface Compensation; Table 17. 8-Bit Hub Interface RCOMP Resistor Values; -Bit Hub Interface Decoupling Guidelines
  • Page 78 – System Bus Ground Plane Reference; Additional Host Bus Guidelines; Minimizing Crosstalk on the AGTL+ Interface; Avoid parallelism between signals on adjacent layers.
  • Page 79 – Additional Considerations; Cable
  • Page 80 – Cable Detection for Ultra ATA/66 and Ultra ATA/100; pull-up resistor to
  • Page 82 – Device-Side Cable Detection; For platforms that must implement device-side detection; be; Figure 47. Device-Side IDE Cable Detection
  • Page 83 – Primary IDE Connector Requirements; Figure 48. Connection Requirements for Primary IDE Connector
  • Page 84 – Secondary IDE Connector Requirements; Figure 49. Connection Requirements for Secondary IDE Connector
  • Page 85 – Figure 50. ICH2 AC’97– Codec Connection
  • Page 86 – AC’97 Audio Codec Detect Circuit and Configuration Options; and R
  • Page 87 – CNR Board; and the
  • Page 88 – CNR
  • Page 89 – Circuit Notes; required; strongly recommended
  • Page 90 – Table 19. Codec Configurations; Communication and Networking Riser (CNR); Figure 55. CNR Interface
  • Page 91 – The basic recommendations are as follows:
  • Page 92 – Implementation
  • Page 93 – Figure 56. USB Data Signals; SB C; Disabling the Native USB Interface of ICH2; Support
  • Page 94 – I/O APIC Design Recommendation
  • Page 95 – Table 20. Pull-Up Requirements for SMBus and SMLink Signals
  • Page 96 – Figure 58. PCI Bus Layout Example; This circuit is not the same as the circuit used for the PIIX4.
  • Page 97 – Crystal; Figure 59. External Circuitry for the ICH RTC; Capacitors
  • Page 98 – RTC Layout Considerations; Minimize the capacitance between Xin and Xout in the routing.; RTC External Battery Connection; Figure 60. Diode Circuit Connecting RTC External Battery; VccRTC
  • Page 99 – RTC External RTCRST Circuit; Figure 61. RTCRST External Circuit for ICH2 RTC
  • Page 100 – RTC Routing Guidelines; Put a ground plane under all external RTC circuitry.; VBIAS DC Voltage and Noise Measurements; Noise on VBIAS must be minimized at; RTC-Well Input Strap Requirements; SPKR Pin Consideration
  • Page 101 – Figure 62. SPKR Circuit; SPKR; ICH2 PIRQ Routing; Table 21. Usage of I/O APIC Interrupt Inputs 16 through 23
  • Page 102 – Figure 63. Example PCI IRQ Routing; LAN Layout Guidelines; Intel developed a dual footprint for the Intel 82562ET and Intel
  • Page 103 – Table 22. LAN Design Guide Section Reference; ICH2 – LAN Interconnect Guidelines; This interface supports both Intel
  • Page 104 – Topologies; LOM/CNR implementation; Interconnect
  • Page 105 – Table 23. Length Requirements for Figure 66; Additional guidelines for this configuration are as follows:; Signal Routing and Layout
  • Page 106 – Consideration; signal integrity requirements may be violated.
  • Page 107 – General LAN Routing Guidelines and Considerations; General Trace Routing Considerations; Keep the maximum separation between differential pairs to 7 mils.; Figure 68. Trace Routing
  • Page 108 – Power and Ground Connections
  • Page 109 – Figure 69. Ground Plane Separation
  • Page 110 – -Layer Board Design; Ground Plane; Unequal length of the two traces within a differential pair; noise which will distort the transmit or receive waveforms.
  • Page 111 – Use of an inferior magnetics module; . The magnetics modules used by Intel have been fully tested; Using an Intel; . It is important to have an approximately 100
  • Page 112 – Table 24. Related Documents
  • Page 113 – Phoneline HPNA Termination; parallel termination should be placed close to the Intel
  • Page 114 – Dimensions; 2562EH component to the magnetics module.; Figure 71. Critical Dimensions for Component Placement; 2562EH Component to Magnetics Module
  • Page 115 – Guidelines for Intel
  • Page 116 – Crystals and Oscillators; any noisy signals in this area.; 2562EM Component Termination Resistors; impedance reflected through the transformer.; component to the magnetics module.
  • Page 117 – Figure 73. Critical Dimensions for Component Placement
  • Page 118 – 2562ET Component to the Magnetics; differential value. These traces also should be symmetric and of; Reducing Circuit Inductance; resistors to
  • Page 119 – Figure 74. Termination Plane; LAN Disable Circuit
  • Page 120 – State; Enabled; Footprint Guidelines; motherboard design. The following guidelines are for the Intel; Figure 76. Dual-Footprint LAN Connect Interface; ICH
  • Page 121 – Figure 77. Dual-Footprint Analog Interface
  • Page 122 – ICH2 Decoupling Recommendations; Table 25. Decoupling Capacitor Recommendation
  • Page 123 – Figure 78. Decoupling Capacitor Layout
  • Page 124 – FWH Flash BIOS Guidelines; In-Circuit FWH Flash BIOS Programming
  • Page 125 – ICH2 Design Checklist; Table 26. PCI Interface
  • Page 126 – Table 27. Hub Interface; Table 28. LAN Interface; Table 29. EEPROM Interface
  • Page 127 – Table 31. Interrupt Interface
  • Page 128 – Table 33. USB Interface
  • Page 129 – Table 34. Power Management; Table 35. Processor Signals
  • Page 130 – Table 36. System Management
  • Page 131 – Table 39. Miscellaneous Signals
  • Page 132 – Circuitry
  • Page 133 – Table 42. ISA Bridge Checklist
  • Page 134 – ICH2 Layout Checklist; Table 44. IDE Interface
  • Page 136 – Table 48. ICH2 Decoupling
  • Page 139 – Advanced System Bus Design; Terminology and Definitions
  • Page 140 – Maximum and Minimum Flight Time.
  • Page 141 – AGTL+ Design Guidelines; Guideline Methodology
  • Page 142 – Initial Timing Analysis; do not; Equation 5. Hold Time; Pentium; Equation 6. Maximum Flight Time; Equation 7. Minimum Flight Time
  • Page 143 – Table 51. AGTL+ Parameters for Example Calculations
  • Page 144 – CLK
  • Page 145 – Calculations; Determine the Desired General Topology, Layout, and Routing; Analysis
  • Page 146 – Monte Carlo Analysis; both; highly recommends
  • Page 147 – Place and Route Board; Layout and Route Board
  • Page 148 – Table 54. Trace Width Space Guidelines; Host Clock Routing; APIC Data Bus Routing
  • Page 149 – Simulation; Interference; before the next rising edge is driven. This results in
  • Page 151 – Figure 76. Test Load vs. Actual System Load; Equation 8. Valid Delay Equation; Flight Time Hardware Validation
  • Page 152 – Requirements
  • Page 153 – Theory; Figure 77. Aggressor and Victim Networks; AC ground plane
  • Page 154 – add; Potential Termination Crosstalk Problems
  • Page 155 – More Details and Insight; Textbook Timing Equations; MECL System Design Handbook
  • Page 156 – Effective Impedance and Tolerance/Variation; Distribution
  • Page 157 – Reference Planes and PCB Stack-Up; It is; that baseboard stack-up be arranged such that AGTL+ signals are; Figure 79. One Signal Layer and One Reference Plane; When it is not possible to route the entire AGTL+ signal on a single V; referenced layer, there are; Figure 80. Layer Switch with One Reference Plane; Signal Layer A
  • Page 158 – Figure 81. Layer Switch with Multiple Reference Planes (Same Type); or multiple planes,; and V; vias as closely as possible and/or; Figure 82. Layer Switch with Multiple Reference Planes
  • Page 159 – Figure 83. One Layer with Multiple Reference Planes; Ground; and ground within the Intel
  • Page 160 – total
  • Page 161 – Region; does not; Figure 84. Overdrive Region and V; Guard Band; Guardband
  • Page 162 – Flight Time Definition and Measurement; Figure 85. Rising-Edge Flight Time Measurement; Overdrive Region
  • Page 163 – Generation; 20E Chipset Platform System Clocks
  • Page 164 – 20E Chipset Platform Clock Distribution
  • Page 165 – 20E Chipset Platform Clock Skews
  • Page 167 – 20E Chipset Platform System Clock Cross-Reference
  • Page 169 – MCH to DRCG; PclkM; signals should change layers together.; Figure 90. Direct RDRAM* Clock Routing Dimensions
  • Page 170 – Channel; Trace Geometry
  • Page 172 – DRCG Impedance Matching Circuit; The values for the; Figure 94. DRCG Impedance Matching Network; channel impedance. For
  • Page 173 – DRCG Layout Example; Figure 95. DRCG Layout Example; AGP Clock Routing Guidelines; Series Termination Resistors for CK133 Clock Outputs
  • Page 174 – Outputs; Table 60. Unused Output Termination; Decoupling Recommendation for CK133 and DRCG
  • Page 175 – DRCG Frequency Selection and the DRCG+; DRCG Frequency Selection Table and Jitter Specification; the existing DRCG device. Two modifications were made to the DRCG+.
  • Page 176 – DRCG+ Frequency Selection Schematic
  • Page 177 – Manufacturing; Requirement; and; Materials; PCB tolerances determine the Z; εεεε
  • Page 178 – Process; Intel’s Impedance Test Methodology; Test Coupon Design Guidelines; Intel Controlled Impedance Design and Test
  • Page 180 – Trace; trace; Do not forget ground floods and stitching.; Impedance Calculation Tools
  • Page 181 – Testing Board Impedance; The; Not Routable
  • Page 183 – System Design Considerations; Delivery
  • Page 184 – Power Delivery of Intel; can be powered only; 20E Chipset Power Delivery Example
  • Page 185 – V Dual Switch; VTT
  • Page 188 – The VCMOS described in the 2.5 V; section for information regarding powering the VCMOS (1.8
  • Page 189 – Q1
  • Page 190 – Option 1: Reduce the Clock Frequency During Initialization; this requires more power.
  • Page 191 – Figure 105. Use a GPO to Reduce DRCG Frequency; DRCG
  • Page 192 – ICH2 Power Plane Split; The following; Figure 106. Example of ICH2 Power Plane Split
  • Page 193 – Thermal Design Power; 20E Chipset Component Thermal Design Power; 20E Chipset Glue Chip); Features
  • Page 194 – Table 64. Glue Chip Vendors
  • Page 195 – Appendix A: Reference Design; Reference Design Feature Set
  • Page 197 – FCPGA 2 RIMM ICH2 REFERENCE SCHEMATICS
  • Page 200 – ITP Test Port Option
  • Page 201 – Clock Synthesizer
  • Page 206 – FWH
  • Page 207 – RIMM Sockets
  • Page 208 – SIO
  • Page 212 – ICH2 AC97 AND CNR LINK STUFFING OPTIONS; Stuffing Option for
  • Page 215 – EH
  • Page 217 – LAN
  • Page 219 – System
  • Page 220 – AGP Connector
  • Page 221 – PCI Connectors
  • Page 223 – IDE Connectors
  • Page 224 – USB Connectors
  • Page 225 – Parallel Port
  • Page 226 – Serial Ports
  • Page 228 – Game Port
  • Page 229 – VRM; VRM requirements are based on VRM8.4 spec .
  • Page 230 – Voltage Regulators
  • Page 232 – Power Connector
  • Page 233 – AGTL Termination
  • Page 235 – Rambus
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Intel

®

820E Chipset


Design Guide

May 2001


Document Number:

298187-003

R

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Summary

Page 3 - Contents; Intel

Intel ® 820E Chipset R Design Guide 3 Contents 1. Introduction ................................................................................................................................ 13 1.1. About This Design Guide ...............................................................................

Page 4 - System Bus Design – Pentium

Intel ® 820E Chipset R 4 Design Guide 2.8.3. 2×/4× Timing Domain Routing Guidelines ................................................... 62 2.8.4. AGP 2.0 Routing Summary ......................................................................... 64 2.8.5. AGP Clock Routing ...............................

Page 6 - Clock Routing Guidelines for Intel

Intel ® 820E Chipset R 6 Design Guide 3.2.3. Pre-Layout Simulation................................................................................ 145 3.2.3.1. Methodology.................................................................................. 145 3.2.3.2. Sensitivity Analysis ...............

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