Xilinx UG078 - Manuals

6 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Preface: About This Guide R Online Document The following conventions are used in this document: Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals ...

8 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Introduction R Features • Independent power supply jacks for VCCINT, VCCO, and VCCAUX • Selectable VCCO-enable pins for each SelectIO™ bank • Configuration port for use with Parallel Cable III and Parallel Cable IV cables •...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 9 UG078 (v1.2) May 24, 2006 Introduction R Figure 1 shows a block diagram of the board. Figure 1: Virtex-4 LX/SX Prototype Platform Block Diagram Virtex-4 DUT Upstream System ACE Interface Connector LEDs UG078_01_101204 DONELED INITLED VBATT PROGRAM U...

10 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R Detailed Description The Virtex-4 prototype platform board is shown in Figure 2 . Each feature is detailed in the numbered sections that follow. 1. Power Switch The board has an onboard power supply ...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 11 UG078 (v1.2) May 24, 2006 Detailed Description R Off Position In the OFF position, the power switch disables all modes of powering the DUT. Power Enable Jumpers For each power supply there are headers marked SUPPLY on one side and JACK on the other...

12 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R 3. Configuration Ports These headers can be used to connect a Parallel Cable III or Parallel Cable IV cable to the board (see Table 2 ) and support all Virtex-4 device configuration modes. See Table ...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 13 UG078 (v1.2) May 24, 2006 Detailed Description R 4. JTAG Chain Jumper J17 provides the ability to have the Virtex-4 in the JTAG chain or remove it from the JTAG chain. Note: The Virtex-4 device must not be in the socket when detecting the ISPROM in...

14 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R 6a. Upstream System ACE Interface Connector The upstream System ACE interface connector, as shown in Figure 4 , can be used to configure the DUT. Any JTAG configuration stream can source this connect...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 15 UG078 (v1.2) May 24, 2006 Detailed Description R 6c. Upstream Interface Connector The upstream interface connector, as shown in Figure 6 , is used to configure the DUT in select map or slave-serial mode. This connector can be sourced by a downstrea...

16 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R 6d. Downstream Interface Connector The downstream interface connector, as shown in Figure 7 , passes serial configuration information to the DUT in the downstream prototype platform board. 7. Prototy...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 17 UG078 (v1.2) May 24, 2006 Detailed Description R 10. Oscillator Sockets The board has four crystal oscillator sockets, all wired for standard LVTTL-type oscillators. These sockets connect to the DUT clock pads as shown in Table 4 and Table 5 . Onbo...

18 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R 11. Differential Clock Inputs In addition to the oscillator sockets, there are eight 50 Ω SMA connectors that allow connection to an external function generator. These connect to the DUT clock pads a...

Virtex-4 LX/SX Prototype Platform www.xilinx.com 19 UG078 (v1.2) May 24, 2006 Detailed Description R 12. DUT Socket The DUT socket contains the user FPGA, referred to as the device under test (DUT). The DUT must be oriented using the P1 indicator on the board. Caution! Failure to insert the device t...

20 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R Table 9: Breakout Clock Pin Connections for FF1148 and FF1513 FF1148 FF1513 Label Clock Name Pin Number Clock Name Pin Number Break o ut A rea IO_L4P_GC_LC_3 E13 IO_L4P_GC_LC_3 J21 IO_L4N_GC_VREF_LC_...

22 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.2) May 24, 2006 Detailed Description R 15. PROGRAM Switch The active-low PROGRAM switch, when pressed, grounds the program pin on the DUT. 16. RESET Switch (Active-Low) The RESET switch connects to a standard I/O pin on the DUT, allowing ...