Xilinx PLB PCI Full Bridge - Manuals

Page 2 - EARL; Features

PLB PCI Full Bridge (v1.00a) 2 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Features • Independent PLB and PCI clocks • 33 MHz, 32-bit PCI bus support • Utilizes two pairs of FIFOs to exploit the separate master and slave PLB IPIF modules. • Includes a master IP module for...

Page 3 - EAR

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 3 Product Specification EAR LY ACCESS default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition is defined only by parameters • Registers include - Interrupt and interrupt enab...

Page 4 - System Reset; Evaluation Version; LogiCore Version 3.0 32-bit PCI Core Requirements

PLB PCI Full Bridge (v1.00a) 4 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS System Reset When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock. Evaluation Version The PLB PCI Bridge is...

Page 5 - Bus Interface Parameters; Address Translation

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 5 Product Specification EAR LY ACCESS core. These documents detail the v3.0 core operation, including configuration cycles, and are available from Xilinx. As required by the LogiCORE v3.0 core, GNT_N must be asserted for two clock cycl...

Page 6 - Example 1; Example 2

PLB PCI Full Bridge (v1.00a) 6 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a remote PLB address space . Figure 2: Translation of Addr...

Page 7 - Example 3

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 7 Product Specification EAR LY ACCESS As in example 1, it is assumed that the parameter C_INCLUDE_BAROFFSET_REG=0, therefore the C_IPIFBAR2PCIBAR_N parameters define the address translation. In this example, where C_IPIFBAR_NUM=4, the ...

Page 14 - PLB PCI Bus Interface I/O Signals; Port

PLB PCI Full Bridge (v1.00a) 14 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS PLB PCI Bus Interface I/O Signals The I/O signals for the PLB PCI Bridge are listed in Table 2 . The interfaces referenced in this table are shown in Figure 1 in the PLB PCI Bridge block diagram. ...

Page 18 - Port and Parameter Dependencies

PLB PCI Full Bridge (v1.00a) 18 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Port and Parameter Dependencies The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters are shown in Table 1. Table 3: PLB PCI Bridge Parameters-Port Dependenci...

Page 22 - Supported PCI Bus Commands; Command

PLB PCI Full Bridge (v1.00a) 22 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Supported PCI Bus Commands The list of commands supported by the LogiCORE PCI interface is provided in Table 4 . G62 C_NUM_IDSEL G49 and G63 G61 and G63 If G61=0, G62 has no meaning. If G61=1, G62...

Page 23 - PLB PCI Bridge Register Descriptions; Register Name

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 23 Product Specification EAR LY ACCESS PLB PCI Bridge Register Descriptions The PLB PCI Bridge contains addressable registers for read/write operations as shown in Table 5 . The base address for these registers is set by the base addre...

Page 24 - Register and Parameter Dependencies; PLB PCI Bridge Interrupt Registers Descriptions; Interrupt Module Specifications

PLB PCI Full Bridge (v1.00a) 24 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Register and Parameter Dependencies The addressable registers in the PLB PCI Bridge depend on the parameter settings shown in Table 6 . Table 6: Register and Parameter Dependencies Register Name P...

Page 25 - Global Interrupt Enable Register Description; Bridge Interrupt Register Description

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 25 Product Specification EAR LY ACCESS Global Interrupt Enable Register Description A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is AND’d with the output to the interrupt controller...

Page 26 - Bridge Interrupt Enable Register Description

PLB PCI Full Bridge (v1.00a) 26 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Bridge Interrupt Enable Register Description The PLB PCI Bridge has interrupt enable features as described in IPSPEC048 PLB Device Interrupt Architecture . Bit assignment in the Bridge Interrupt E...

Page 27 - PLB PCI Bridge Reset Register Description; Name

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 27 Product Specification EAR LY ACCESS PLB PCI Bridge Reset Register Description The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset module can be found in the Processor IP Reference Guide . The ...

Page 28 - Configuration Address Port Register Description; Configuration Data Port Register Description; Bus Number/Subordinate Bus Number Register Description

PLB PCI Full Bridge (v1.00a) 28 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Configuration Address Port Register Description The Configuration Address Port Register exists only if the bridge is configured with PCI host bridge configuration functionality (i.e., C_INCLUDE_PC...

Page 29 - IPIFBAR2PCIBAR_N High-Order Bits Register Description

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 29 Product Specification EAR LY ACCESS bus number. The highest subordinate bus number is also an 8-bit value. The fields are defined in Table 12 . Reset clears all bits. Table 12: Bus Number/Subordinate Bus Number Register Bit Definiti...

Page 31 - Host Bridge Device Number Register Description

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 31 Product Specification EAR LY ACCESS Writing 0xFEDC0000 to IPIFBAR2PCIBAR_1 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus would yield 0xFEDC1123 on the PCI bus. Writing...

Page 32 - PLB PCI Transactions

PLB PCI Full Bridge (v1.00a) 32 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS PLB PCI Transactions The following subsections discuss details of the following types of transactions for the PLB PCI bridge to realize data throughputs as high as 132 MB/sec. This assumes the PLB...

Page 33 - PCI Initiator Command

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 33 Product Specification EAR LY ACCESS For all the transactions listed above, the following design requirements are specified: • Both PCI and PLB clocks will be independent global buffers. For Virtex-4, RCLK must also be driven by glob...

Page 35 - Abnormal Terminations

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 35 Product Specification EAR LY ACCESS mode). • If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that presented on the PLB bus. If the PLB transaction is not a burst (i.e., PLB_rdBurst is not high), a s...

Page 37 - Abnormal condition; PLB Master Initiates a Write Request to a PCI Target

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 37 Product Specification EAR LY ACCESS Table 17 summarizes the abnormal conditions with which a PCI target can respond and how the response is translated to the PLB master. Table 17: Response of PLB Master/v3.0 Initiator read of a remo...

Page 40 - Abnormal

PLB PCI Full Bridge (v1.00a) 40 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS transaction. The PLB PCI Bridge performs retries up to a parameterized number of times as described earlier for the condition of disconnects with/without data. A time-out cannot occur during a sin...

Page 41 - PCI Initiator Initiates a Read Request of a PLB Slave

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 41 Product Specification EAR LY ACCESS PCI Initiator Initiates a Read Request of a PLB Slave This section discusses the operation of a remote PCI initiator asserting both single and multiple read commands to read data from a remote PLB...

Page 44 - PCI Initiator Initiates a Write Request to a PLB Slave

Table 19: Response to PCI initiator doing a read of a remote PLB slave that terminates the transfer with an abnormal condition on PLB bus Abnormal condition Memory Read Memory Read Multiple SERR Target abort by v3.0 core, but completes PLB transaction. Flush FIFOs and assert PLB-side Read SERR inter...

Page 46 - Configuration Transactions

PLB PCI Full Bridge (v1.00a) 46 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS defined number of retries are not successful, the PCI interrupt will be strobed. Data in the write buffer is flushed when the PCI interrupt is strobed. • If during a write command a PLB slave asse...

Page 47 - Configuration Space Header

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 47 Product Specification EAR LY ACCESS bridge is not used. As with Memory and IO data transactions, byte addressing integrity is maintained in configuration transfers across the bus. When host bridge configuration functionality is impl...

Page 50 - Design Implementation; Design Tools

PLB PCI Full Bridge (v1.00a) 50 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS subordinate buses. Device numbers are independent for each PLB PCI bridge instantiated, but bus numbering must be monotonically increasing for all primary buses and their subordinate buses. Abnorm...

Page 51 - Design Debug; Design Contraints

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 51 Product Specification EAR LY ACCESS Design Debug The OBP PCI Bridge has a test vector output (PCI_monitor) to facilitate system debug (i.e., adding an ILA to a system). The test vector allows monitoring the PCI bus and is the output...

Page 54 - Target Technology

PLB PCI Full Bridge (v1.00a) 54 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS # TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ; TIMEGRP "PCI_PADS_B" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS&#...

Page 55 - generate netlist

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 55 Product Specification EAR LY ACCESS one IDELAYCTRl without LOC constraints, the tools will replicate the primitive throughout the design. Replicating the primitive has the undesirable results of higher power consumption, higher powe...

Page 57 - Device Utilization and Performance Benchmarks; Parameter Values

PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www.xilinx.com 57 Product Specification EAR LY ACCESS the ucf-file in the implementation directory of the bridge directory to verify that the constraints are included. Alternatively, the user can include all constraints in the top-level ucf-file. Whe...

Page 58 - Reference Documents; Revision History; Date

PLB PCI Full Bridge (v1.00a) 58 www.xilinx.com DS508 March 21, 2006 Product Specification EARL Y ACCESS Reference Documents The following documents contain reference information important to understanding the PLB PCI Bridge design: • Processor IP Reference Guide • Xilinx LogiCORE PCI Interface v3.0 ...