Xilinx ML361 Virtex-II Pro - Manuals

6 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 R Figure 4-29: Data Signals from Memory to FPGA (55 Ω Impedance) . . . . . . . . . . . . . . . . . 59 Figure 4-30: Clock Signals with 45 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ...

ML361 Virtex-II Pro Memory Board www.xilinx.com 7 UG060 (v1.2) November 8, 2007 Chapter 1: Introduction Chapter 2: Architecture Table 2-1: GPIO Header 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2-2: GPIO Header 2 . . . . . ....

ML361 Virtex-II Pro Memory Board www.xilinx.com 9 UG060 (v1.2) November 8, 2007 R Preface About This Guide This document describes the design of the ML361 Virtex-II Pro™ DDR400/PC3200 Memory Board, which connects a Virtex-II Pro FPGA to DDR memories. Guide Contents This manual contains the following...

10 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Preface: About This Guide R Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this document: Online Docum...

ML361 Virtex-II Pro Memory Board www.xilinx.com 11 UG060 (v1.2) November 8, 2007 R Chapter 1 Introduction Overview The ML361 Virtex-II Pro DDR400/PC3200 Memory Board provides a communications platform between a Virtex-II Pro FPGA and high-speed double-data-rate (DDR) memories with operating speeds u...

12 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 1: Introduction R The ML361 demonstrates a 64-/72-bit interface to a 128 MByte, 200 MHz DDR SDRAM DIMM, a 72-bit interface to five 256 Mbit, 200 MHz DDR SDRAM components, and an additional 8-bit interface to a 2...

ML361 Virtex-II Pro Memory Board www.xilinx.com 13 UG060 (v1.2) November 8, 2007 R Chapter 2 Architecture This chapter provides functional descriptions of the major blocks within the ML361 board design. For more detailed information on the design, refer to the schematics, which are located at http:/...

14 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 2: Architecture R Block Descriptions This section describes the major blocks of the ML361 board. FPGA The ML361 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged in a 1152-pin BGA pack...

ML361 Virtex-II Pro Memory Board www.xilinx.com 15 UG060 (v1.2) November 8, 2007 Block Descriptions R 166 MHz LVDS Test Clock The LVDS test clock is a Pletronics SM7745DW-100.0M clock oscillator with a single-ended output. This oscillator runs at 166 MHz ± 50 PPM with an operating voltage of 2.5 V ±...

16 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 2: Architecture R II DIP Switch One eight-position DIP switch is connected to the FPGA I/Os as shown in Table 2-3 . These switches can be used to externally pull up or pull down any signal on the FPGA. Seven-Seg...

ML361 Virtex-II Pro Memory Board www.xilinx.com 17 UG060 (v1.2) November 8, 2007 Block Descriptions R LEDs Four green LEDs connect to the FPGA I/Os as indicated in Table 2-6 . The LEDs are active Low. Push Buttons The ML361 board contains four momentary push buttons. Their functions are as follows: ...

18 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 2: Architecture R Power Power Distribution The ML361 board uses a 5V input voltage source to generate all the on-board voltages (1.3V, 1.5V, 2.6V, and 3.3V, and the 2.5V for the MGTs) Input Voltage The input vol...

ML361 Virtex-II Pro Memory Board www.xilinx.com 19 UG060 (v1.2) November 8, 2007 Block Descriptions R PROMs The ML361 board contains XCF04S PROMs that can be used to program the Virtex-II Pro FPGA. The PROM operates with a 3.3 V core voltage and a 2.5 V I/O voltage.

ML361 Virtex-II Pro Memory Board www.xilinx.com 21 UG060 (v1.2) November 8, 2007 R Chapter 3 Electrical Requirements Power Consumption Table 3-1 lists the operating voltages, maximum currents, and power consumption used by the ML361 board devices. Refer to Appendix A, “Related Documentation,” for mo...

22 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 3: Electrical Requirements R FPGA Internal Power Budget The following tables show the power consumption values inside the FPGA based on the complete DDR design. These results are derived using the Xilinx Power E...

ML361 Virtex-II Pro Memory Board www.xilinx.com 25 UG060 (v1.2) November 8, 2007 R Chapter 4 Signal Integrity Recommendations and Simulations This chapter provides the following information: • Summary of the termination schemes for various signals ( “Termination and Transmission Line Summaries,” pag...

26 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Terminations and Transmission Lines for DDR Components Data and Clock Signals (DQ, DQS, DM, CLK) For these DDR signals, the terminations at the FPGA and memo...

ML361 Virtex-II Pro Memory Board www.xilinx.com 27 UG060 (v1.2) November 8, 2007 Duty Cycle Summary R • There is a total of 4.9 inches of trace from the FPGA to the last component assuming the DDR memory components are 0.6 inch apart. Microstrip is used to model the transmission lines for the first ...

ML361 Virtex-II Pro Memory Board www.xilinx.com 29 UG060 (v1.2) November 8, 2007 IBIS Simulations R IBIS Simulations This section summarizes various simulations run on the Memory Board using IBIS. It defines the test conditions and provides color-coded screen captures of the results. The resulting s...

30 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R c. Address and Control Signals - Address and Control Signals with 45 Ω Transmission Lines Measured at First DDR Component (Typical) - Address and Control Sig...

ML361 Virtex-II Pro Memory Board www.xilinx.com 31 UG060 (v1.2) November 8, 2007 IBIS Simulations R Data Signal Simulations All data signal simulations below have the following test conditions for typical, slow weak, and fast strong cases: • Topology for data signals: 50 Ω Transmission lines • At me...

ML361 Virtex-II Pro Memory Board www.xilinx.com 35 UG060 (v1.2) November 8, 2007 IBIS Simulations R Eye Diagram Figure 4-5 shows the eye diagram for the data signals from the FPGA to the last memory component. X-Ref Target - Figure 4-5 Figure 4-5: Eye Diagram for Data from the FPGA to Last Memory Co...

36 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Data Signals from the Last Memory to the FPGA: Measured at FPGA The simulations in this subsection test the data signals from the last memory to the FPGA. Si...

38 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Fast Strong Corner Case for Data from Memory to the FPGA For the fast strong case simulation, the resulting duty cycle is 48.38/51.76. Figure 4-8 shows the s...

ML361 Virtex-II Pro Memory Board www.xilinx.com 39 UG060 (v1.2) November 8, 2007 IBIS Simulations R Eye Diagram for Data Signal Measured at the FPGA Figure 4-9 shows the eye diagram for the data signals from the FPGA to the last memory component. X-Ref Target - Figure 4-9 Figure 4-9: Eye Diagram for...

40 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Clock Signal Simulations The simulations in this subsection test the unidirectional clock signals from the FPGA to memory. Simulations were performed for the...

ML361 Virtex-II Pro Memory Board www.xilinx.com 41 UG060 (v1.2) November 8, 2007 IBIS Simulations R Typical Case for Clock Signals For the typical case simulation, the resulting duty cycle is 48.1/52.04. Figure 4-11 shows the simulation screen capture for this case. X-Ref Target - Figure 4-11 Figure...

42 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Slow Weak Case for Clock Signals For the slow weak case simulation, the resulting duty cycle is 48.66/51.48. Figure 4-12 shows the simulation screen capture ...

ML361 Virtex-II Pro Memory Board www.xilinx.com 43 UG060 (v1.2) November 8, 2007 IBIS Simulations R Fast Strong Case for Clock Signals For the fast strong case simulation, the resulting duty cycle is 48.1/51.48. Figure 4-13 shows the simulation screen capture for this case. X-Ref Target - Figure 4-1...

44 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Eye Diagram of Clock Signals at Memory Figure 4-14 shows the eye diagram for the clock signals at memory. X-Ref Target - Figure 4-14 Figure 4-14: Eye Diagram...

ML361 Virtex-II Pro Memory Board www.xilinx.com 45 UG060 (v1.2) November 8, 2007 IBIS Simulations R Address and Control Signal Simulations The simulations in this subsection test the unidirectional address and control signals from the FPGA to five DDR memory components. Simulations were performed on...

46 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Typical Case Simulation at All Memory Components Figure 4-16 shows the simulation screen capture for the typical case for all memory components. X-Ref Target...

ML361 Virtex-II Pro Memory Board www.xilinx.com 47 UG060 (v1.2) November 8, 2007 IBIS Simulations R Typical Case Simulation at First DDR Component For the typical case simulation at the first DDR component, the resulting duty cycle is 48.94/51.2. Figure 4-17 shows the simulation screen capture for t...

48 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Slow Weak Corner Case Simulation at First DDR Component For the slow weak corner case simulation at the first DDR component, the resulting duty cycle is 49.2...

ML361 Virtex-II Pro Memory Board www.xilinx.com 49 UG060 (v1.2) November 8, 2007 IBIS Simulations R Fast Strong Corner Case Simulation at First DDR Component For the fast strong corner case simulation at the first DDR component, the resulting duty cycle is 48.66/51.2. Figure 4-19 shows the simulatio...

50 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Typical Case Simulation at Last DDR Component For the typical case simulation at the last DDR component, the resulting duty cycle is 49.22/50.92. Figure 4-20...

ML361 Virtex-II Pro Memory Board www.xilinx.com 51 UG060 (v1.2) November 8, 2007 IBIS Simulations R Slow Weak Case Simulation at Last DDR Component For the slow weak case simulation at the last DDR component, the resulting duty cycle is 49.22/50.63. Figure 4-21 shows the simulation screen capture fo...

52 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Fast Strong Corner Case Simulation at Last DDR Component For the fast strong corner case simulation at the last DDR component, the resulting duty cycle is 49...

ML361 Virtex-II Pro Memory Board www.xilinx.com 53 UG060 (v1.2) November 8, 2007 IBIS Simulations R Typical Case Simulation at Middle DDR Component For the typical case simulation at the middle DDR component, the resulting duty cycle is 49.23/51.49. Figure 4-23 shows the simulation screen capture fo...

54 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Slow Weak Corner Case Simulation at Middle DDR Component For the slow weak corner case simulation at the middle DDR component, the resulting duty cycle is 49...

ML361 Virtex-II Pro Memory Board www.xilinx.com 55 UG060 (v1.2) November 8, 2007 IBIS Simulations R Fast Strong Corner Case Simulation at Middle DDR Component For the fast strong corner case simulation at the middle DDR component, the resulting duty cycle is 48.94/51.2. Figure 4-25 shows the simulat...

56 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Simulations with 10% Tolerance on the Transmission Line Impedance These simulations illustrate the typical cases for data, clock, and address and control sig...

ML361 Virtex-II Pro Memory Board www.xilinx.com 57 UG060 (v1.2) November 8, 2007 IBIS Simulations R Data Signals from the Last DDR Memory to the FPGA with 55 Ω Transmission Line Impedance For the typical case simulation from the last DDR component to the FPGA, the resulting duty cycle is 46.4/52.62....

58 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Data Signals from FPGA to the Last DDR Memory Component with 45 Ω Transmission Line Impedance For the typical case simulation from the FPGA to the last DDR c...

ML361 Virtex-II Pro Memory Board www.xilinx.com 59 UG060 (v1.2) November 8, 2007 IBIS Simulations R Data Signals from Memory to the FPGA with 55 Ω Transmission Line Impedance For the typical case simulation from memory to the FPGA, the resulting duty cycle is 48.66/51.48. Figure 4-29 shows the simul...

60 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Clock Signals This subsection provides the clock simulation results for the following typical cases: • With 45 Ω transmission line impedance • With 55 Ω tran...

62 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Chapter 4: Signal Integrity Recommendations and Simulations R Address/Control Signals This subsection provides the address and control simulation results for the following typical cases: • With 45 Ω transmission line im...

ML361 Virtex-II Pro Memory Board www.xilinx.com 63 UG060 (v1.2) November 8, 2007 IBIS Simulations R Address and Control Signals with 55 Ω Transmission Lines Measured at the First DDR Component For the typical case simulation with a 55 Ω transmission line impedance measured at the first DDR component...

ML361 Virtex-II Pro Memory Board www.xilinx.com 65 UG060 (v1.2) November 8, 2007 R Chapter 5 Board Layout Guidelines This chapter provides information on decoupling capacitors, ground signals, and PCB layout. Decoupling Guidelines This section lists the decoupling capacitors used with the major comp...

ML361 Virtex-II Pro Memory Board www.xilinx.com 67 UG060 (v1.2) November 8, 2007 Providing Additional Ground Pins R Providing Additional Ground Pins Additional Ground pins can be added by tying unused and no connect pins to GND. Board Stackup Guidelines Table 5-4 shows a suggested stackup of a 16-la...

ML361 Virtex-II Pro Memory Board www.xilinx.com 69 UG060 (v1.2) November 8, 2007 R Appendix A Related Documentation This appendix provides references to documents and web pages for components on the ML361 board. • Xilinx, Inc. ♦ Virtex-II Pro X™ Platform FPGAs http://www.xilinx.com/bvdocs/publicatio...

ML361 Virtex-II Pro Memory Board www.xilinx.com 71 UG060 (v1.2) November 8, 2007 R Appendix B FPGA Pinout Table B-1 summarizes the pinout of the XC2VP20FF1152-6 FPGA in the ML361 board. The slice coordinates mentioned in Table B-1 refer to the RPM grid coordinates corresponding to the respective I/O...