Xilinx 3.2 - Manuals

CAN Getting Started Guide www.xilinx.com 5 UG186 April 19, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Figure 3-1: Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-2...

CAN Getting Started Guide www.xilinx.com 7 UG186 April 19, 2010 Preface About This Guide The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through impl...

8 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Preface: About This Guide Online Document The following linking conventions are used in this document: Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the...

CAN Getting Started Guide www.xilinx.com 9 UG186 April 19, 2010 Chapter 1 Introduction The LogiCORE™ IP CAN v3.2 core is a compact, full-featured targeted design platform that conforms to ISO 11898-1 , CAN2.0A and CAN2.0B standards. Bit rates of up to 1 Mbps are supported. The core size can be optim...

10 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Chapter 1: Introduction Recommended Design Experience Although the CAN core is a fully-verified targeted design platform, the challenge associated with implementing a complete CAN design varies, depending on the application requirement...

CAN Getting Started Guide www.xilinx.com 11 UG186 April 19, 2010 Chapter 2 Licensing the Core This chapter provides instructions for obtaining a license for the CAN core, which you must do before using the core in your designs. The CAN core is provided under the terms of the Xilinx LogiCORE Site Lic...

12 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Chapter 2: Licensing the Core Full The Full license key is available when you purchase the core and provides full access to all core functionality both in simulation and in hardware, including: • Gate-level functional simulation suppor...

CAN Getting Started Guide www.xilinx.com 13 UG186 April 19, 2010 Chapter 3 Quick Start Example Design This chapter provides instructions to generate a CAN core quickly, run the design through implementation with the Xilinx tools, and simulate the example design using the provided demonstration test ...

14 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Chapter 3: Quick Start Example Design Generating the Core This section describes how to generate a CAN core with default values using the Xilinx CORE Generator™ tool. To generate the core: 1. Start the CORE Generator tool. For help sta...

CAN Getting Started Guide www.xilinx.com 15 UG186 April 19, 2010 Implementing the Example Design 7. In the Component Name field, enter a name for the core instance. This example uses the name quickstart . 8. After selecting the parameters from the GUI screens, click Finish. The core and its supporti...

16 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Chapter 3: Quick Start Example Design Functional Simulation This section provides instructions for running a functional simulation of the CAN core using either VHDL or Verilog. Functional simulation models are provided when the core is...

CAN Getting Started Guide www.xilinx.com 17 UG186 April 19, 2010 Chapter 4 Detailed Example Design This chapter provides detailed information about the example design, including a description of files and the directory structure generated by the Xilinx CORE Generator™ software, the purpose and conte...

CAN Getting Started Guide www.xilinx.com 23 UG186 April 19, 2010 Implementation Scripts Implementation Scripts Note: Present only with a Full license. The implementation script is either a shell script(.sh) or batch file (.bat) that processes the example design through the Xilinx tool flow. It is lo...

CAN Getting Started Guide www.xilinx.com 25 UG186 April 19, 2010 Demonstration Test Bench Demonstration Test Bench Figure 4-2 illustrates the demonstration test bench. Test Bench Functionality The demonstration test bench is a straightforward VHDL or Verilog file to exercise the example design and t...

26 www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010 Chapter 4: Detailed Example Design • Five messages are written in sequence: 1. The first message is written to the TXHPB and is a standard data frame. 2. The second message is written to the TX FIFO and is a standard data frame. 3. The...

CAN Getting Started Guide www.xilinx.com 27 UG186 April 19, 2010 Demonstration Test Bench • After the fourth message is transmitted and received, the Interrupt Enable Register is written to enable interrupts for TXOK, RXOK and TXBFLL. This register is read from and the value read is compared with th...