Page 3 - NOTES FOR CMOS DEVICES; circuitry. Each unused pin should be connected to V; or GND with a resistor, if it is considered
User’s Manual U12978EJ3V0UD 3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricit...
Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .
User’s Manual U12978EJ3V0UD 4 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country.Diversion contrary to the law of that country is prohibited. T h e i n f o r m a t i o n i n t h i s d o c u m e n t i s c u r r...
Page 5 - Regional Information; Device availability
User’s Manual U12978EJ3V0UD 5 Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power ...
Page 6 - Major Revisions in This Edition; μμμμ
User’s Manual U12978EJ3V0UD 6 Major Revisions in This Edition Page Contents Deletion of CU-type and GB-3BS type packages Throughout Deletion of indication “under development” for µ PD78F9801 p. 21 Modification of operating ambient temperature when flash memory is written in 1.1 Features p. 27 Additi...
Page 7 - INTRODUCTION
User’s Manual U12978EJ3V0UD 7 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the µ PD789800 Subseries and who design and develop its application systems and programs. Target products: • µ PD789800 Subseries: µ PD789800 and µ PD78F9801 Purpose This manu...
Page 8 - Related Documents; However, preliminary versions are not marked as such.; Documents Related to Devices; Documents Related to Flash Memory Writing
User’s Manual U12978EJ3V0UD 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD789800 Subseries User’s Manual This manual 78K/0S Se...
Page 9 - Other Related Documents; Document Name; Caution
User’s Manual U12978EJ3V0UD 9 Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Q...
Page 10 - TABLE OF CONTENTS
User’s Manual U12978EJ3V0UD 10 TABLE OF CONTENTS CHAPTER 1 GENERAL.......................................................................................................................... 21 1.1 Features ..................................................................................................
Page 21 - CHAPTER 1 GENERAL; Ordering Information; Remark
User’s Manual U12978EJ3V0UD 21 CHAPTER 1 GENERAL 1.1 Features • On-chip USB functions • Implements a USB (Universal Serial Bus) by connecting to Hub and Host. • Transfer speed: 1.5 Mbps (at 6.0 MHz operation with system clock) • On-chip regulator • Controls the USB port voltage by using a bus power ...
Page 22 - USBDP; REGC
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 22 1.4 Pin Configuration (Top View) • 44-pin plastic LQFP (10 × 10) µ PD789800GB- ××× -8ES, µ PD78F9801GB-8ES P04 P03 P02 P01 P00 V DD1 V SS1 P17 P16 P15 P14 NC P13 P12 P11 P10 P47/KR07 P46/KR06 P45/KR05 P44/KR04 P43/KR03 P42/KR02 USBDP USBDM IC (V PP ) ...
Page 23 - VFD (Vacuum Fluorescent Display) is referred to as FIP; documents, but the functions of the two are same.
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 23 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. 52-pin SIO + resistance division method LCD (24 × 4) 8-bit A/D + internal voltage boosting method LCD (23 × 4) PD789327 LCD d...
Page 24 - The major differences between subseries are shown below.; Series for General-Purpose and LCD Drive; Note
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 24 The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Timer V DD Function Subseries ROM Capacity (Bytes) 8-Bit 16-Bit Watch WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O MIN.Value Remarks µ PD789046 16 K 1 c...
Page 25 - Series for ASSP
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 25 Series for ASSP Timer V DD Function Subseries ROM Capacity (Bytes) 8-Bit 16-Bit Watch WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O MIN.Value Remarks USB µ PD789800 8 K 2 ch − − 1 ch − − 2 ch (USB: 1ch) 31 4.0 V − Invertercontrol µ PD789842 8 K to 16 ...
Page 26 - The parenthesized values apply to the
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 26 1.6 Block Diagram Key return 0 8-bit timer 00 8-bit timer/event counter 01 Watchdog timer Regulator USBfunction 0 Serial interface 1 Interrupt control Port 0 Port 1 Port 2 Port 4 System control 78K/0SCPU core ROMFlash memory RAM P00 to P07 P10 to P17 ...
Page 27 - An outline of the timer is shown below.
CHAPTER 1 GENERAL User’s Manual U12978EJ3V0UD 27 1.7 Functions Product Item µ PD789800 µ PD78F9801 Internal memory ROM Mask ROM 8 KB Flash memory 16 KB High-speed RAM 256 bytes Minimum instruction execution time 0.33 µ s/1.33 µ s (at 6.0 MHz operation with system clock) Instruction set • 16-bit oper...
Page 29 - CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS User’s Manual U12978EJ3V0UD 29 (2) Non-port pins Pin Name I/O Function After Reset Alternate Function INTP0 Input External interrupt request input for which valid edge (rising and/or falling edge) can be specified Input P26/TI01/TO01 KR00 to KR07 Input Input for detecting key...
Page 30 - These are the serial data I/O pins of the serial interface.
CHAPTER 2 PIN FUNCTIONS User’s Manual U12978EJ3V0UD 30 2.2 Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to the input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up...
Page 31 - The following operation modes can be specified in 1-bit units.; RESET; This pin inputs an active-low system reset signal.; USBDM; These pins are positive power supply pins.
CHAPTER 2 PIN FUNCTIONS User’s Manual U12978EJ3V0UD 31 2.2.4 P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, port 4 functions a...
Page 33 - Pin I/O Circuits and Recommended Connection of Unused Pins; Figure 2-1 shows the configuration of each type of I/O circuit.
CHAPTER 2 PIN FUNCTIONS User’s Manual U12978EJ3V0UD 33 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of I/O circuit. Table 2-1. Type of Pi...
Page 35 - CHAPTER 3 CPU ARCHITECTURE; The
User’s Manual U12978EJ3V0UD 35 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789800 Subseries can access 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1. Memory Map ( µµµµ PD789800) Reserved Internal ROM 8,192 × 8 bits Internal high-speed RAM 256 × 8 bits Special fu...
Page 37 - The internal high-speed RAM is also used as a stack.
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 37 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The following areas are allocated to the internal program memory space. (1) Vec...
Page 40 - Processor Registers; Figure 3-5. Configuration of Program Counter; PC; RESET input sets the PSW to 02H.; Figure 3-6. Configuration of Program Status Word
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 40 3.2 Processor Registers The µ PD789800 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence, statuses and stack memory. A program...
Page 41 - maskable interrupts are all disabled.
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 41 (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When 0, the IE flag is set to the interrupt disabled status (DI), and interrupt requests other than non- maskable interrupts are all dis...
Page 42 - RAM area can be set as the stack area.; Figure 3-7. Configuration of Stack Pointer; SP
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 42 (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Configuration of Stack Pointer SP15 SP SP14 SP13 SP12 SP11...
Page 45 - 6-bit access is possible only in short direct addressing.
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 45 Table 3-2. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits FF00H Port 0 P0 R/W √ √ — 00H FF01H Port 1 P1 √ √ — FF02H Port 2 P2 √ √ — FF04H Po...
Page 48 - Instruction Address Addressing; 8K/0S Series Instruction User’s; displacement value is treated as signed two’s complement data (
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 48 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched e...
Page 49 - In case of CALL !addr16 and BR !addr16 instructions
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 49 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 a...
Page 51 - Operand Address Addressing; during instruction execution.
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 51 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data...
Page 54 - MOV A, C When selecting the C register for r
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 54 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code or function name in the inst...
Page 55 - in an instruction code.; Identifier
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 55 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register ...
Page 56 - In the case of PUSH DE
CHAPTER 3 CPU ARCHITECTURE User’s Manual U12978EJ3V0UD 56 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive n...
Page 57 - CHAPTER 4 PORT FUNCTIONS; CHAPTER 2 PIN FUNCTIONS
User’s Manual U12978EJ3V0UD 57 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789800 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information ...
Page 59 - Port Configuration; Ports consists the following hardware.; Parameter
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 59 4.2 Port Configuration Ports consists the following hardware. Table 4-2. Configuration of Port Parameter Configuration Control registers Port mode register (PMm: m = 0 to 2, 4) Pull-up resistor option register (PU0) Port output mode register (P...
Page 62 - This port to set to the input mode when the RESET signal is input.; Pull-up resistor option register 0
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 62 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can...
Page 65 - Figure 4-7. Block Diagram of P23 and P24; WR; Output latch
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 65 Figure 4-7. Block Diagram of P23 and P24 Internal bus WR PU0 RD WR PORT WR PM PU02 Output latch (P23, P24) PM23, PM24 V DD0 P-ch P23, P24 Selector PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 2 read signal WR: Port 2 ...
Page 66 - Port output mode register 1
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 66 Figure 4-8. Block Diagram of P25 RD V DD0 P25 WR POM1 WR PU0 WR PORT WR PM Output latch (P25) PM25 PU02 P-ch P-ch N-ch V DD0 POM125 Internal bus Selector POM1: Port output mode register 1 PU0: Pull-up resistor option register 0 PM: Port mode re...
Page 69 - Registers Controlling Port Function; The following three types of registers control the ports.
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 69 4.3 Registers Controlling Port Function The following three types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM4) • Pull-up resistor option register (PU0) • Port output mode registers (POM0, POM1) (1) Port mode regist...
Page 70 - Don’t care
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 70 Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Secondary Function Name Input/Output P26 TO01 Output 0 0 TI01 Input 1 × INTP0 Input 1 × P40 to P47 Note KR00 to KR07 Input 1 × Note Set key return mode regis...
Page 71 - RESET input sets P0M0 and POM1 to 00H.; POM0 selects the output mode for a port in 8-bit units.; POM1 selects the output mode for P25 or P26 in 1-bit units.
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 71 (3) Port output mode registers (POM0 and POM1) The port output mode registers (POM0 and POM1) are used to switch from CMOS output to N-ch open-drain output for port 0, port 1, pin P25, and pin P26. Set POM0 and POM1 with a 1-bit or 8-bit memory...
Page 72 - Port Function Operation; latch can be output from the pins of the port.; output buffer is off.
CHAPTER 4 PORT FUNCTIONS User’s Manual U12978EJ3V0UD 72 4.4 Port Function Operation The operation of a port differs depending on whether the port is set to the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port ...
Page 73 - of system clock oscillator is used.; System clock oscillator; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 5-1. Configuration of Clock Generator; Item; Figure 5-1. Block Diagram of Clock Generator
User’s Manual U12978EJ3V0UD 73 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. •••• System clock oscillator This circuit oscillates at 6.0 MHz. Os...
Page 74 - CHAPTER 5 CLOCK GENERATOR; Register Controlling Clock Generator; The clock generator is controlled by the following register.; Figure 5-2. Format of Processor Clock Control Register; PCC; : system clock oscillation frequency
CHAPTER 5 CLOCK GENERATOR User’s Manual U12978EJ3V0UD 74 5.3 Register Controlling Clock Generator The clock generator is controlled by the following register. • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and sets the of division ratio....
Page 75 - System Clock Oscillators; Figure 5-3. External Circuit of System Clock Oscillator; OPEN
CHAPTER 5 CLOCK GENERATOR User’s Manual U12978EJ3V0UD 75 5.4 System Clock Oscillators 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal resonator (6.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case,...
Page 76 - Examples of incorrect resonator connection; Figure 5-4 shows examples of incorrect resonator connection.; PORTn; (c) Wiring near high fluctuating current; (d) Current flowing through ground line of oscillator
CHAPTER 5 CLOCK GENERATOR User’s Manual U12978EJ3V0UD 76 5.4.2 Examples of incorrect resonator connection Figure 5-4 shows examples of incorrect resonator connection. Figure 5-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line V SS0 X1 X2 V SS0 X1 X2 PORT...
Page 77 - Clock Generator Operation; System clock f; Clock to peripheral hardware
CHAPTER 5 CLOCK GENERATOR User’s Manual U12978EJ3V0UD 77 Figure 5-4. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched V SS0 X1 X2 5.4.3 Frequency divider The frequency divider divides the output of the system clock oscillator (f X ) to generate various clocks. 5.5 Clock Gener...
Page 78 - Changing Setting of CPU Clock; Time required for switching CPU clock; is used for the duration of several instructions after that (see; Table 5-2. Maximum Time Required for Switching CPU Clock; The following figure illustrates how the CPU clock switches.; which oscillation stabilization (2; operation can be selected.
CHAPTER 5 CLOCK GENERATOR User’s Manual U12978EJ3V0UD 78 5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after th...
Page 79 - CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U12978EJ3V0UD 79 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.1 Functions of 8-Bit Timer/Event Counters 00 and 01 The 8-bit timer/event counters (TM00 and TM01) have the following functions. • Interval timer (TM00 and TM01) • External event counter (TM01 only) • Square wave output ...
Page 80 - A square wave of arbitrary frequency can be output.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 80 (3) Square wave output A square wave of arbitrary frequency can be output. Table 6-3. Square Wave Output Range of 8-Bit Timer/Event Counter 01 Minimum Pulse Width Maximum Pulse Width Resolution 2 4 /f X (2.67 µ s) 2 12 /f ...
Page 81 - RESET input sets CR0n undefined.; This is an 8-bit register used to count pulses.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 81 Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 01 Internal bus 8-bit compare register 01 (CR01) Match TO01/P26/INTP0/TI01 INTTM01 f X /2 4 f X /2 8 TI01/P26 /INTP0/TO01 Selector Clear 8-bit timer counter 01 (TM01) ...
Page 82 - Registers Controlling 8-Bit Timer/Event Counters 00 and 01; -bit timer mode control registers 00 and 01 (TMC00 and TMC01); : System clock oscillation frequency
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 82 6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01 The following two types of registers are used to control 8-bit timer/event counters 00 and 01. • 8-bit timer mode control registers 00 and 01 (TMC00 and TMC01)...
Page 83 - TMC01 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 83 (2) 8-bit timer mode control register 01 (TMC01) TMC01 determines whether to enable or disable 8-bit timer counter 01 (TM01), specifies the count clock for the 8-bit timer/event counter, and controls the operation of the o...
Page 84 - PM2 is set by a 1-bit or 8-bit memory manipulation instruction.; Figure 6-5. Format of Port Mode Register 2; Symbol
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 84 (3) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P26/TO01/INTP0/TI01 pin for timer output, set P26 and the output latch of P26 to 0. When P26/TO01/INTP0/TI01 pin is used ...
Page 85 - and
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 85 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 6.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00 and ...
Page 86 - Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00; t where N = 00H to FFH
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 86 Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00 Clear Clear Interrupt acknowledged Interrupt acknowledged Count starts Interval time Interval time Interval time Count clock TM00 count value CR00 TCE00 INTTM00...
Page 87 - TI01 pin input
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 87 6.4.2 Operation as external event counter (timer 01 only) The external event counter counts the number of external clock pulses input to the TI01/P26/INTP0/TO01 pin by using timer counter 01 (TM01). To operate the 8-bit ti...
Page 88 - ) and enable output of TO01 by setting; Minimum Pulse Width
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 88 6.4.3 Operation as square-wave output (timer 01 only) The 8-bit timer/event counter can generate output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 01 (CR01) ...
Page 90 - Count pulse; Figure 6-11. Timing of External Event Counter Operation
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 User’s Manual U12978EJ3V0UD 90 6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01 (1) Error on starting timer An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8-bit timer counters 00 and...
Page 91 - Inadvertent Loop
User’s Manual U12978EJ3V0UD 91 CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer Th...
Page 92 - CHAPTER 7 WATCHDOG TIMER; Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 7-3. Configuration of Watchdog Timer
CHAPTER 7 WATCHDOG TIMER User’s Manual U12978EJ3V0UD 92 7.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 7-3. Configuration of Watchdog Timer Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figu...
Page 93 - Registers Controlling Watchdog Timer; This register sets the watchdog timer count clock.; Figure 7-2. Format of Timer Clock Select Register 2
CHAPTER 7 WATCHDOG TIMER User’s Manual U12978EJ3V0UD 93 7.3 Registers Controlling Watchdog Timer The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register set...
Page 94 - RESET input sets the WDTM to 00H.; Figure 7-3. Format of Watchdog Timer Mode Register; started, it cannot be stopped by any means other than RESET input.; Cautions
CHAPTER 7 WATCHDOG TIMER User’s Manual U12978EJ3V0UD 94 (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. The WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets th...
Page 95 - Watchdog Timer Operation; Inadvertent Loop Detection Time
CHAPTER 7 WATCHDOG TIMER User’s Manual U12978EJ3V0UD 95 7.4 Watchdog Timer Operation 7.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time in...
Page 96 - intervals specified by a count value set in advance.; Interval Time
CHAPTER 7 WATCHDOG TIMER User’s Manual U12978EJ3V0UD 96 7.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at ...
Page 97 - CHAPTER 8 USB FUNCTION
User’s Manual U12978EJ3V0UD 97 CHAPTER 8 USB FUNCTION 8.1 USB Overview The USB (Universal Serial Bus) is suitable for connecting personal computers and external devices such as audio equipment, keyboards, pointing devices, and telephones. Two data transfer rates, 12 Mbps and 1.5 Mbps, are provided. ...
Page 98 - USB Function Features; The features of the on-chip USB function provided for the; USB Function Configuration; The USB function consists of the following hardware.; Table 8-1. Configuration of USB Function
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 98 8.2 USB Function Features The features of the on-chip USB function provided for the µ PD789800 Subseries are described below. (1) Video display devices and human interface devices are assumed to be the target applications. For this reason, only E...
Page 99 - Figure 8-2. Block Diagram of USB Function; See
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 99 Figure 8-2. Block Diagram of USB Function Internal bus Internal bus USBDP USBDM • Handshake packet• SYNC packet USB clock Overflow INTUSBTM f X INTUSBRD Start USB receiver enable register (USBMOD) Data/handshake packet receive mode register (URXM...
Page 100 - System clock oscillation frequency
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 100 Figure 8-3. Block Diagram of USB Timer Internal bus UWDERR INTUSBTM f X USBCLK RESUME RX Note Clear circuit Clock controller Shift register In high-speed mode In low-speed mode DATATX SETORX JUDGE TX Note JUDGE TOKEN Note TX MASTER EN Note SETRX...
Page 101 - bank switching ID detection buffer operation
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 101 (1) Receive bank switching ID detection buffer (internal buffer) This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID during packet reception and determines the store bank of a packet. ...
Page 102 - USBRTP is read with an 8-bit memory manipulation instruction.; Figure 8-4. Configuration of Receive Token Bank; USBPOW address
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 102 (3) Receive token bank (a) Receive token PID (USBRTP) This is the receive token packet ID area. The data input to the token PID compare register (TIDCMP) is stored here. USBRTP is read with an 8-bit memory manipulation instruction. RESET input s...
Page 103 - USBRD is read with an 8-bit memory manipulation instruction.; Figure 8-5. Configuration of Receive Data Bank; The operation during reception appears as follows.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 103 (4) Receive data bank (a) Receive data PID (USBRD) This is the receive data packet ID area. The data input to the data/handshake PID compare register (DIDCMP) is stored here. USBRD is read with an 8-bit memory manipulation instruction. RESET inp...
Page 104 - RESET input makes both USBTD0 and USBTD1 undefined.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 104 (5) Transmit data banks 0 and 1 (a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1) USBTD0 and USBTD1 correspond to the transmit buffer 0 ID area and transmit buffer 1 ID area, respectively. USBTD0 and USBTD1 store DATA0 (C3H) or DATA1 (4BH)...
Page 105 - USBPO; The operation during transmission appears as follows.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 105 Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1) Data area (8 bytes) USBPO W address ID area USBPOB address USBTD1 Symbol 07H 06H 05H 04H 03H 02H 01H USBT10 USBT11 USBT12 USBT13 USBT14 USBT15 USBT16 USBT17 30H 00H 31H 32H 33H 34H 35H...
Page 107 - 0H must be set by software when an USB reset is received.; Figure 8-8. Configuration of TIDCMP and ADRCMP
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 107 (9) Token address compare register (ADRCMP) This register sets the address specified from the host during control transfer. If this register value and the address area of the receive token bank (bits 0 to 6 of receive token address L (USBRAL)) m...
Page 109 - Registers Controlling USB Function; Figure 8-10. Format of USB Receiver Enable Register
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 109 8.4 Registers Controlling USB Function The following nine registers are used to control the USB function. • USB receiver enable register (USBMOD) • Data/handshake packet receive mode register (URXMOD) • Packet receive status register (RXSTAT) • ...
Page 110 - Figure 8-11. Format of Data/Handshake Packet Receive Mode Register; immediately when returning from the bus suspend mode.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 110 Figure 8-11. Format of Data/Handshake Packet Receive Mode Register Symbol 6 7 5 4 3 <2> <1> <0> 0 0 0 0 0 RESMOD DINTEN DWRMSK RESMOD USB reset signal detection mode setting 0 1 FF66H Address URXMOD After reset 00H R/W R/W Reje...
Page 111 - This register indicates the receive status of each packet.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 111 (3) Packet receive status register (RXSTAT) This register indicates the receive status of each packet. Bits 0 to 2 (TOSTAT, DASTAT, and HSSTAT) are flags that indicate that a token packet, data packet, or handshake packet is currently being rece...
Page 112 - Figure 8-12. Format of Packet Receive Status Register; Bits 0 to 2: read only
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 112 Figure 8-12. Format of Packet Receive Status Register Symbol 6 7 5 4 3 2 1 0 UWDERR RESMRX SE0RX URESRX EOPRX HSSTAT DASTAT TOSTAT UWDERR USB timer inadvertent program loop detection 0 1 FF67H Address RXSTAT After reset 00H R/W R/W No USB timer ...
Page 114 - Figure 8-14. Format of Token Packet Receive Result Store Register; If SETRX is set to 1, the following occurs.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 114 Figure 8-14. Format of Token Packet Receive Result Store Register Symbol <6> <7> <5> <4> <3> <2> <1> <0> CRC5ER TBITER TBYER END1RX END0RX ADRRST TIDRST SETRX CRC5ER CRC error detection (5-bit mode...
Page 117 - (a) Transmit reservation for Endpoint 0 and IN token packet
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 117 Figure 8-16. Format of Handshake Packet Transmit Reservation Register (2/2) ACKEN ACK packet transmit reservation flag after data packet reception 0 1 No data is transmitted. ACK handshake is transmitted when all the following conditions are sat...
Page 118 - (b) Transmit reservation for Endpoint1 and IN token packet
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 118 Table 8-3. Conditions in Transmit Reservation (2/2) (b) Transmit reservation for Endpoint1 and IN token packet Type of Reservation DT01EN DT11EN E1STEN E1NAEN Transmit reservation of data in transmit buffer 0 1 0 0 0 Transmit reservation of data...
Page 121 - REMWUP is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 8-19. Format of Remote Wakeup Control Register
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 121 (9) Remote wake-up control register (REMWUP) This register transmits the Resume signal to perform remote wakeup. Remote wakeup must be performed after confirming that bus idle has continued longer than 5 ms. REMWUP is set with a 1-bit or 8-bit m...
Page 122 - USB Function Operation; inadvertent program loop detection of the USB clock.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 122 8.5 USB Function Operation 8.5.1 USB timer operation The USB timer is a 7-bit counter that performs time management during packet transmission and reception and inadvertent program loop detection of the USB clock. The USB timer has two modes: hi...
Page 124 - INTUSBTM occurred
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 124 Figure 8-20. Flowchart of USB Timer Operation (2/2) 2 INTUSBTM occurred High-speed mode overflow? 3 N Y N Y 1 Next SYNC detected? USB timer start (high-speed mode)
Page 125 - Figure 8-21. Flow Chart of Remote Wakeup Control Operation; Bit 2 of remote wakeup control register (REMWUP)
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 125 8.5.2 Remote wakeup control operation Figure 8-21. Flow Chart of Remote Wakeup Control Operation Idle state Y N Y 10 ms to 15 ms elapsed? N Resume output started? Y N A ← 00000111B PULLEN = 1 WAKEUP = 1 PULLDP = 0 PULLDM = 1 PULLDP = 0 PULLDM = ...
Page 126 - Figure 8-22. Configuration of Remote Wakeup Control; TXEN; SEP, SEM disable signal
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 126 Notes 1. Be sure to follow the exact instruction sequence when the Resume signal (“K” state) is output. SET1 REMWUP.3 ; (PULLDM ← 1) CLR1 REMWUP.2 ; (PULLDP ← 0) MOV A, #00000111B ; (A ← 00000111B) SET1 REMWUP.1 ; (PULLEN ← 1) SET1 REMWUP.0 ; (W...
Page 127 - Interrupt Request from USB Function; Table 8-4. List of Sources of Interrupts from USB Function
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 127 8.6 Interrupt Request from USB Function 8.6.1 Interrupt sources Interrupt request sources generated by the USB function fall into the following five categories. Table 8-4. List of Sources of Interrupts from USB Function Interrupt Source Type of ...
Page 128 - This is an interrupt to release the STOP mode.; Figure 8-24. Timing of INTUSBRE Generation; INTUSBRE
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 128 (3) Data/handshake packet transmit interrupt (INTUSBST) Upon EOP detection during data/handshake packet transmission, an interrupt request signal is generated and an interrupt request flag (USBSTIF) is set. (4) USB timer overflow interrupt (INTU...
Page 130 - USB Function Control; Relationship between packets and operation modes
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 130 8.7 USB Function Control 8.7.1 Relationship between packets and operation modes The relationship between packets and operation modes in the USB function is as follows. (1) Control transfer (OUT) (Transfer byte count: 8 bytes or less) Request Ope...
Page 132 - counting during this period.
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 132 (3) Control transfer (IN) (Transfer byte count: 8 bytes or less) Request Operation of hostcontroller IN packet SETUP DATA0 ACK Packet from host controller Packet from PD789800 Setup stage Data stage IN reception ACK IN DATA1 • ACK transmission• ...
Page 136 - (1) USB token packet reception interrupt servicing
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 136 8.7.2 Interrupt servicing flow (1) USB token packet reception interrupt servicing INTUSBRT occurrence RETI Receive error occurred? Receive token is OUT? Waiting for OUT token? OUT to ENDPOINT 1? Receive token is SETUP? Receive token is unplanned...
Page 138 - INTUSBTM occurrence
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 138 (3) USB timer inadvertent program loop detection interrupt servicing INTUSBTM occurrence RETI Processing for each operation mode when ACK is not received and for when DATA is not received after receiving OUT
Page 140 - USB Function Internal Circuit Operations; TBYER: Bit 5 of token packet receive result store register (TRXRSL)
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 140 8.8 USB Function Internal Circuit Operations 8.8.1 Operation of transmit/receive pointer Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (1/7) (1) Token packet reception (1/2) Y Y Y N N Y Y EOP Y N N 1 Y Y N N Y EOP Y N N EOP 1 2 Id...
Page 142 - Data/handshake packet receive byte number counter
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 142 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (3/7) (2) Data/Handshake packet reception (1/2) N Y Y Y N Y N EOP Y Y N 1 Y EOP Y N N N Y 2 Idle state Set USBPOW to 10H USBPOB increment USBPOW increment Set USBPOB to 00H Transmit/re...
Page 144 - DTXCO0, DTXCO1: Data packet transmit byte number counter
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 144 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (5/7) (3) Data packet transmit (1/2) Y Y Transmit buffer N Handshake Y Y N N 1 N Y Y Y N N 1 2 Idle state Set USBPOW to 7FH USBPOB increment Set USBPOW to n0H Set USBPOB to 00H Bit rea...
Page 147 - Receive bank switching ID detection buffer operation; Bit 0 of packet receive status register (RXSTAT)
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 147 8.8.2 Receive bank switching ID detection buffer operation Figure 8-26. Flowchart of Receive Bank Switching ID Detection Buffer Operation Y Y Y 01B 00B N Idle state Idle state 2-bit store & shift 1-bit store & shift Set buffer to 00H Bit...
Page 148 - Figure 8-27. Timing of Sync Detection/USBCLK Detector Operation; The USB clock starts operating at the falling edge of f
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 148 8.8.3 Sync detection/USBCLK detector operation This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In addition, it contains an NRZI decoder that decodes receive packets and detects the last bit ...
Page 149 - Sync detection
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 149 Figure 8-29. Flowchart of Sync Detection/USBCLK Detector Operation N Y N Y N Y Y N Idle state USB clock oscillation start Detect last Sync bit Receive next bit Receive next bit Output 0 from NRZI decoder Output 0 from NRZI decoder Output 1 from ...
Page 150 - This circuit performs NRZI encoding of data to be transmitted.; Figure 8-30. Timing of NRZI Encoder Operation; Figure 8-31. Flow Chart of NRZI Encoder Operation
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 150 8.8.4 NRZI encoder operation This circuit performs NRZI encoding of data to be transmitted. Figure 8-30. Timing of NRZI Encoder Operation Data before encoding USB clock generation NRZI encoding Transmit packet Sync pattern Data/handshake packet ...
Page 151 - “logic 0” simultaneously with the increment disable signal.; Figure 8-32. Timing of Bit Stuffing/Strip Controller Operation
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 151 8.8.5 Bit stuffing/strip controller operation This circuit counts the number of “logic 1” of transmit/receive packets. If six successive logic 1s are detected, it outputs an increment disable signal to the transmit/receive pointer (USBPOB). Duri...
Page 152 - Figure 8-33. Flow Chart of Bit Stuffing Control Operation
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 152 Figure 8-33. Flow Chart of Bit Stuffing Control Operation Y Y Y N N Idle state Idle state Transmit bit input Shift bit stuffing register Disable save of next transmit bit Reset bit stuffing register Disable USBPOB increment Transmission start? T...
Page 153 - Figure 8-34. Flow Chart of Bit Strip Control Operation
CHAPTER 8 USB FUNCTION User’s Manual U12978EJ3V0UD 153 Figure 8-34. Flow Chart of Bit Strip Control Operation Y Y Y N N Idle state Idle state Receive bit input Shift bit stuffing register Receive bit input Bit stuffing error output Disable USBPOB increment Reception start? Receive bit = 1? N Y Y N B...
Page 154 - Serial interface 10 has the following two modes.
User’s Manual U12978EJ3V0UD 154 CHAPTER 9 SERIAL INTERFACE 10 9.1 Functions of Serial Interface 10 Serial interface 10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out. It enables a reduction...
Page 155 - CHAPTER 9 SERIAL INTERFACE 10; Configuration of Serial Interface 10; Serial interface 10 consists of the following hardware.; Table 9-1. Configuration of Serial Interface 10; synchronization with the serial clock.
CHAPTER 9 SERIAL INTERFACE 10 User’s Manual U12978EJ3V0UD 155 9.2 Configuration of Serial Interface 10 Serial interface 10 consists of the following hardware. Table 9-1. Configuration of Serial Interface 10 Item Configuration Register Transmit/receive shift register 10 (SIO10) Control register Seria...
Page 156 - Figure 9-1. Block Diagram of Serial Interface 10
CHAP T E R 9 S E R IA L I N T E RFACE 10 U s er’s Manual U12978E J3V 0 U D 156 Figure 9-1. Block Diagram of Serial Interface 10 Internal bus CSIE10 TPS100 DIR10 Serial operation moderegister 10 (CSIM10) CSCK10 Transmit/receive shift register 10 (SIO10) Serial clock counter Clock controller F/F Inter...
Page 157 - Register Controlling Serial Interface 10; The following register is used to control serial interface 10.; Figure 9-2. Format of Serial Operation Mode Register 10
CHAPTER 9 SERIAL INTERFACE 10 User’s Manual U12978EJ3V0UD 157 9.3 Register Controlling Serial Interface 10 The following register is used to control serial interface 10. • Serial operation mode register 10 (CSIM10) (1) Serial operation mode register 10 (CSIM10) This register is used to control seria...
Page 158 - Table 9-2. Operating Mode Settings of Serial Interface 10; Can be used as port function.
CHAPTER 9 SERIAL INTERFACE 10 User’s Manual U12978EJ3V0UD 158 Table 9-2. Operating Mode Settings of Serial Interface 10 (1) Operation stop mode CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI10 P21/SO10 P20/SCK10 CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function 0 × × × Note ...
Page 159 - Operation of Serial Interface 10; Serial interface 10 provides the following two modes.; Serial operation mode register 10 (CSIM10); CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 9 SERIAL INTERFACE 10 User’s Manual U12978EJ3V0UD 159 9.4 Operation of Serial Interface 10 Serial interface 10 provides the following two modes. • Operation stop mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, th...
Page 161 - End of transfer; two conditions are satisfied.
CHAPTER 9 SERIAL INTERFACE 10 User’s Manual U12978EJ3V0UD 161 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmit/receive shift register 10 (SIO1...
Page 162 - CHAPTER 10 REGULATOR; Supports power-saving mode, reducing power consumption in mode.; Figure 10-1. Block Diagram of Regulator and USB Driver/Receiver; voltage, connect the REGC pin to V
User’s Manual U12978EJ3V0UD 162 CHAPTER 10 REGULATOR The µ PD789800 incorporates a regulator that powers the USB driver/receiver. The features are as follows. • Generates V REG (3.3 ± 0.3 V) from V DD0 , V DD1 (4.0 to 5.5 V) and outputs it to the REGC pin. • Supports power-saving mode, reducing powe...
Page 163 - The following two types of interrupt functions are used.; Interrupt Sources and Configuration
User’s Manual U12978EJ3V0UD 163 CHAPTER 11 INTERRUPT FUNCTIONS 11.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does no undergo interrupt priority control and is given top priority ove...
Page 164 - CHAPTER 11 INTERRUPT FUNCTIONS; is the highest priority and 10 is the lowest.
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 164 Table 11-1. Interrupt Source List Type of Interrupt Priority Note 1 Interrupt Source Name Trigger Nonmaskable - INTWDT Watchdog timer overflow (when watchdog timer mode 1 is selected) Internal 0004H (A) Maskable 0 INTWDT Watchdog timer o...
Page 165 - Figure 11-1. Basic Configuration of Interrupt Function
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 165 Figure 11-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Interrupt request Vector tableaddress generator Standby release signal (B) Internal maskable interrupt MK IF IE Internal bus Interrup...
Page 166 - Registers Controlling Interrupt Function; Interrupt request flag registers 0 and 1 (IF0 and IF1); Table 11-2. Flags Corresponding to Interrupt Request Signals
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 166 11.3 Registers Controlling Interrupt Function The following five registers are used to control the interrupt functions. • Interrupt request flag registers 0 and 1 (IF0 and IF1) • Interrupt mask flag registers 0 and 1 (MK0 and MK1) • Exte...
Page 167 - RESET input sets IF0 and IF1 to 00H.; Figure 11-2. Format of Interrupt Request Flag Register
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 167 (1) Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknow...
Page 168 - RESET input sets MK0 and MK1 to FFH.; Figure 11-3. Format of Interrupt Mask Flag Register; This register is used to set the valid edge of INTP0.; Figure 11-4. Format of External Interrupt Mode Register 0
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 168 (2) Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets...
Page 169 - Figure 11-5. Configuration of Program Status Word
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 169 (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped here. Besides...
Page 170 - KRM00 is set with a 1-bit an 8-bit memory manipulation instruction.; Figure 11-6. Format of Key Return Mode Register 00; Register that selects the pin used for falling edge input.
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 170 (5) Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (rising edge of port 4). KRM00 is set with a 1-bit an 8-bit memory manipulation instruction. Bit 0 (KRM000) is set in 4-bit units for the...
Page 171 - Interrupt Servicing Operation
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 171 11.4 Interrupt Servicing Operation 11.4.1 Non-maskable interrupt acknowledgment operation The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and t...
Page 172 - WDTM: Watchdog timer mode register
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 172 Figure 11-8. Flowchart of Non-Maskable Interrupt Request Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer No WDT overflows No Yes Reset processing No Yes Yes Interrupt request is generated Interrupt servici...
Page 173 - Maskable interrupt acknowledgment operation; from the one assigned the highest priority.; Figure 11-11. Interrupt Acknowledgment Program Algorithm
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 173 11.4.2 Maskable interrupt acknowledgment operation A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in th...
Page 174 - Figure 11-13. Timing of Interrupt Request Acknowledgment
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 174 Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r) Clock CPU MOV A,r Saving PSW and PC, and jump to interrupt handling Interrupt servicing program Interrupt 8 clocks When an interrupt request flag (xxIF) is gen...
Page 176 - Figure 11-14. Example of Multiplexed Interrupt Servicing; acknowledged after INTxx servicing is completed.
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 176 Figure 11-14. Example of Multiplexed Interrupt Servicing Example 1. Acknowledging multiplexed interrupts INTyy EI Main processing EI INTyy processing INTxx processing RETI IE = 0 INTxx RETI IE = 0 The interrupt request INTyy is acknowled...
Page 177 - instructions include:
CHAPTER 11 INTERRUPT FUNCTIONS User’s Manual U12978EJ3V0UD 177 11.4.4 Interrupt request hold If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instructi...
Page 178 - or for intermittent operations.
User’s Manual U12978EJ3V0UD 178 CHAPTER 12 STANDBY FUNCTION 12.1 Standby Function and Configuration 12.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruct...
Page 179 - CHAPTER 12 STANDBY FUNCTION; Register controlling standby function; OSTS is set with an 8-bit memory manipulation instruction.
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 179 12.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an...
Page 180 - Standby Function Operation; The HALT mode is set by executing the HALT instruction.
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 180 12.2 Standby Function Operation 12.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 12-1. HALT Mode Operation Status Item HALT M...
Page 181 - (a) Releasing by unmasked interrupt request
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 181 (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be ackn...
Page 182 - Figure 12-3. Releasing HALT Mode by RESET Input; Table 12-2. Operation After Release of HALT Mode
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 182 (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 12-3. Releasing HAL...
Page 183 - The STOP mode is set by executing the STOP instruction.; Operation is enabled only when TI01 is selected as the count clock.
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 183 12.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to V DD to suppress the current leakage of the ...
Page 184 - The STOP mode can be released by the following two sources.; mode is acknowledged.
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 184 (2) Releasing STOP mode The STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be ac...
Page 185 - Figure 12-5. Releasing STOP Mode by RESET Input
CHAPTER 12 STANDBY FUNCTION User’s Manual U12978EJ3V0UD 185 (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 12-5. Releasing STOP Mode by RESET Input STOP instruction RESET s...
Page 186 - CHAPTER 13 RESET FUNCTION; oscillation stabilization time just after reset release.; s or more to the RESET pin.
User’s Manual U12978EJ3V0UD 186 CHAPTER 13 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by inadvertent program loop time detected by watchdog timer External and internal reset have no functional differe...
Page 187 - Figure 13-2. Reset Timing by RESET Input
CHAPTER 13 RESET FUNCTION User’s Manual U12978EJ3V0UD 187 Figure 13-2. Reset Timing by RESET Input X1 RESET Internal reset signal Port pin During normaloperation Delay Delay Hi-Z Reset period(oscillation stops) Normal operation(reset processing) Oscillationstabilizationtime wait Figure 13-3. Reset T...
Page 188 - statuses become undefined.
CHAPTER 13 RESET FUNCTION User’s Manual U12978EJ3V0UD 188 Table 13-1. Hardware Status After Reset (1/2) Hardware Status After Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Un...
Page 190 - CHAPTER 16 ELECTRICAL SPECIFICATIONS
User’s Manual U12978EJ3V0UD 190 CHAPTER 14 µµµµ PD78F9801 The µ PD78F9801 is a product that substitutes flash memory for the internal ROM of the mask ROM version. The differences between the µ PD78F9801 and the mask ROM versions are shown in Table 14-1. Table 14-1. Differences Between µµµµ PD78F9801...
Page 191 - CHAPTER 14; Flash Memory Characteristics; Programming using flash memory has the following advantages.; USB is supported by Flashpro IV only.; Figure 14-1. Environment for Writing Program to Flash Memory; Host machine
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 191 14.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µ PD78F9801 mount...
Page 192 - ELECTRICAL SPECIFICATIONS
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 192 14.1.2 Communication mode Use the communication mode shown in Table 14-2 to perform communication between the dedicated flash programmer and µ PD78F9801. Table 14-2. Communication Mode List TYPE Setting Note 1 Communication Mode COMM PORT SIO...
Page 193 - voltage before starting programming.
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 193 Figure 14-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK Note GND V PP V DD0 , V DD1 RESET SCK10 SI10 SO10 X1 V SS0 , V SS1 PD78F9801 µ (b) Pseudo-3-wire ...
Page 194 - Pin Connection List; voltage must be supplied before programming is started.; Pin must be connected.
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 194 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the µ PD78F9801. For details, refer to the manual of Flashpro III/Flashpro IV. Table 14-3. Pin Connection L...
Page 195 - Pin Connection Example; Connection pin of dedicated flash programmer; Serial Interface
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 195 14.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and ...
Page 196 - Signal conflict; device or set the other device to the output high impedance status.; Abnormal operation of other device; input signals to the other device are ignored.; Figure 14-6. Abnormal Operation of Other Device
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 196 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other devic...
Page 198 - Connection of adapter for flash writing
CHAPTER 14 µµµµ PD78F9801 User’s Manual U12978EJ3V0UD 198 14.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 14-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O 12 13 14 1...
Page 200 - CHAPTER 15 INSTRUCTION SET; Operand identifiers and description methods
User’s Manual U12978EJ3V0UD 200 CHAPTER 15 INSTRUCTION SET This chapter lists the instruction set of the µ PD789800 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instruction User’s Manual (U11047E) . 15.1 Operation 15.1.1 ...
Page 201 - Description of “flag operation” column
CHAPTER 15 INSTRUCTION SET User’s Manual U12978EJ3V0UD 201 15.1.2 Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE ...
Page 202 - One instruction clock cycle is one CPU clock cycle (f; ) selected by the processor clock control
CHAPTER 15 INSTRUCTION SET User’s Manual U12978EJ3V0UD 202 15.2 Operation List Mnemonic Operands Bytes Clocks Operation Flag Z AC CY MOV r,#byte 3 6 r ← byte saddr,#byte 3 6 (saddr) ← byte sfr,#byte 3 6 sfr ← byte A,r Note 1 2 4 A ← r r,A Note 1 2 4 r ← A A,saddr 2 4 A ← (saddr) saddr,A 2 4 (saddr) ...
Page 207 - Instructions Listed by Addressing Type
CHAPTER 15 INSTRUCTION SET User’s Manual U12978EJ3V0UD 207 15.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand 1st Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte]...
Page 210 - CHAPTER 16 ELECTRICAL SPECIFICATIONS; Absolute Maximum Ratings (T
User’s Manual U12978EJ3V0UD 210 CHAPTER 16 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 25 °°°° C) Parameter Symbol Conditions Rating Unit V DD − 0.3 to +6.5 V Supply voltage V PP µ PD78F9801 only Note 1 − 0.3 to +10.5 V Input voltage V I − 0.3 to V DD + 0.3 Note 2 V Output voltage V O ...
Page 211 - Indicates only oscillator characteristics. Refer to
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 211 System Clock Oscillation Circuit Characteristics (T A = −−−− 40 to +85 °°°° C, V DD = 4.0 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillator frequency (f X ) Note 1 6.0 6.0 6.0 MHz Crystal X...
Page 212 - DC Characteristics (T; RL is the resistance connected to the bus line.
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 212 DC Characteristics (T A = −−−− 40 to +85 °°°° C, V DD = 4.0 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Per pin − 1 mA Output current, high I OH Total for all pins − 15 mA Per pin 10 mA Output current, low I OL ...
Page 214 - AC Characteristics; CL is the capacitance of the USBDM and USBDP output lines.
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 214 AC Characteristics (1) Basic operations (T A = −−−− 40 to +85 °°°° C, V DD = 4.0 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit When PCC = 00H (f X = 6.0 MHz) 0.333 0.333 0.333 µ s Cycle time (minimum instruction executi...
Page 215 - Bit 4 of serial operation mode register 10 (CSIM10); CL is the capacitance of the SO output line.
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 215 (b) 3-wire serial I/O mode (T A = −−−− 40 to +85 °°°° C, V DD = 4.0 to 5.5 V) (i) SCK10 ...Internal clock output (when f X = 6.0 MHz) Parameter Symbol Conditions MIN. TYP. MAX. Unit When TPS100 Note 1 = 0 667 667 667 ns SCK10 cycle...
Page 216 - AC Timing Measurement Points (Except X1 Input and USB Function); Clock timing; TI Timing
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 216 AC Timing Measurement Points (Except X1 Input and USB Function) 0.8V DD 0.2V DD 0.8V DD 0.2V DD Measurementpoints Clock timing 1/f X t XL t XH X1 input V IH3 (MIN.) V IL3 (MAX.) TI Timing TI01 t TIL t TIH 1/f TI Interrupt Input Tim...
Page 217 - Serial Transfer Timing; Transmission differential signal jitter; Next bit; USB reset width
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 217 Serial Transfer Timing USB function: USBDM and USBDP rise/fall time USBDM, USBDP t R 0.1V DD 0.9V DD t F Transmission differential signal jitter Next bit Bit following the next bit 667 ns 1,333 ns t UDJ1 t UDJ2 USBDM, USBDP Differe...
Page 218 - unstable upon the start of oscillation.; Data Hold timing (STOP Mode Release by RESET )
CHAPTER 16 ELECTRICAL SPECIFICATIONS User’s Manual U12978EJ3V0UD 218 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = −−−− 40 to +85 °°°° C) Item Symbol Conditions MIN. TYP. MAX. Unit Data hold supply voltage V DDDR 4.0 5.5 V Release signal set time t SREL 0 µ s Release...
Page 219 - CHAPTER 17 PACKAGE DRAWINGS; detail of lead end; NOTE
User’s Manual U12978EJ3V0UD 219 CHAPTER 17 PACKAGE DRAWINGS 33 34 22 44 1 12 11 23 44 PIN PLASTIC LQFP (10x10) I T E M M I L L I M E T E R S N Q 0 . 1 ± 0 . 0 5 0 . 1 0 S44GB-80-8ES-2 J I H N A 1 2 . 0 ± 0 . 2 B 1 0 . 0 ± 0 . 2 C 1 0 . 0 ± 0 . 2 D 1 2 . 0 ± 0 . 2 F G H 1 . 0 0 . 3 7 1 . 0 I J K 0 . ...
Page 220 - CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS; Semiconductor Device Mounting
User’s Manual U12978EJ3V0UD 220 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS The µ PD789800 Subseries should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (...
Page 221 - APPENDIX A DEVELOPMENT TOOLS; Support of the PC98-NX series
User’s Manual U12978EJ3V0UD 221 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789800 Subseries. Figure A-1 shows the development tools. • Support of the PC98-NX series Unless otherwise stated, the µ PD789800 Subseries, which is su...
Page 222 - C library source file is not included in the software package.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978EJ3V0UD 222 Figure A-1. Development Tools Language processing software · Assembler package · C compiler package · Device file · C library source file Note 1 Debugging software · Integrated debugger · System simulator Host machine (PC or EWS) Interface...
Page 223 - A.1 Software Package; Software package; in the part number differs depending on the OS used.; A.2 Language Processing Software
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978EJ3V0UD 223 A.1 Software Package Software tools for development of the 78K/0S Series are combined in this package. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files SP78K0S Software package Part number: µ S ××××...
Page 224 - A.3 Control Software
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978EJ3V0UD 224 Remark ×××× in the part number differs depending on the host machine and operating system to be used. µ S ×××× RA78K0S µ S ×××× CC78K0S ×××× Host Machine OS Supply Medium AB13 Japanese Windows 3.5" 2HD FD BB13 English Windows AB17 Japa...
Page 225 - The TGB-044SAP is a product made by TOKYO ELETECH CORPORATION.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978EJ3V0UD 225 A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software of an application system using the 78K/0S Series. Supports a integrated debugger (ID78K0S-NS). Used in combination with ...
Page 227 - A.7 Notes on Target System Design; Emulation board; Target system; TGB-044SAP is a product of TOKYO ELETECH CORPORATION.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978EJ3V0UD 227 A.7 Notes on Target System Design Figures A-2 and A-3 show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when...
Page 229 - APPENDIX B REGISTER INDEX
User’s Manual U12978EJ3V0UD 229 APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) 8-bit compare register 00 (CR00) .......................................................................................................................... 81 8-bit compare register 01 (C...
Page 233 - APPENDIX C REVISION HISTORY
User’s Manual U12978EJ3V0UD 233 APPENDIX C REVISION HISTORY The revision history is described below. The “Applied to” column indicates the chapters in each edition. (1/2) Edition Major Revisions from Previous Edition Applied to: Deletion of description “under development” for µ PD789800, since it ha...
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