NEC switch - Manual

NEC switch

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Table of Contents:

  • Page 3 – NOTES FOR CMOS DEVICES; circuitry. Each unused pin should be connected to V; or GND with a resistor, if it is considered
  • Page 4 – s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .
  • Page 5 – Regional Information; Device availability
  • Page 6 – Major Revisions in This Edition; μμμμ
  • Page 7 – INTRODUCTION
  • Page 8 – Related Documents; However, preliminary versions are not marked as such.; Documents Related to Devices; Documents Related to Flash Memory Writing
  • Page 9 – Other Related Documents; Document Name; Caution
  • Page 10 – TABLE OF CONTENTS
  • Page 21 – CHAPTER 1 GENERAL; Ordering Information; Remark
  • Page 22 – USBDP; REGC
  • Page 23 – VFD (Vacuum Fluorescent Display) is referred to as FIP; documents, but the functions of the two are same.
  • Page 24 – The major differences between subseries are shown below.; Series for General-Purpose and LCD Drive; Note
  • Page 25 – Series for ASSP
  • Page 26 – The parenthesized values apply to the
  • Page 27 – An outline of the timer is shown below.
  • Page 29 – CHAPTER 2 PIN FUNCTIONS
  • Page 30 – These are the serial data I/O pins of the serial interface.
  • Page 31 – The following operation modes can be specified in 1-bit units.; RESET; This pin inputs an active-low system reset signal.; USBDM; These pins are positive power supply pins.
  • Page 33 – Pin I/O Circuits and Recommended Connection of Unused Pins; Figure 2-1 shows the configuration of each type of I/O circuit.
  • Page 35 – CHAPTER 3 CPU ARCHITECTURE; The
  • Page 37 – The internal high-speed RAM is also used as a stack.
  • Page 40 – Processor Registers; Figure 3-5. Configuration of Program Counter; PC; RESET input sets the PSW to 02H.; Figure 3-6. Configuration of Program Status Word
  • Page 41 – maskable interrupts are all disabled.
  • Page 42 – RAM area can be set as the stack area.; Figure 3-7. Configuration of Stack Pointer; SP
  • Page 45 – 6-bit access is possible only in short direct addressing.
  • Page 48 – Instruction Address Addressing; 8K/0S Series Instruction User’s; displacement value is treated as signed two’s complement data (
  • Page 49 – In case of CALL !addr16 and BR !addr16 instructions
  • Page 51 – Operand Address Addressing; during instruction execution.
  • Page 54 – MOV A, C When selecting the C register for r
  • Page 55 – in an instruction code.; Identifier
  • Page 56 – In the case of PUSH DE
  • Page 57 – CHAPTER 4 PORT FUNCTIONS; CHAPTER 2 PIN FUNCTIONS
  • Page 59 – Port Configuration; Ports consists the following hardware.; Parameter
  • Page 62 – This port to set to the input mode when the RESET signal is input.; Pull-up resistor option register 0
  • Page 65 – Figure 4-7. Block Diagram of P23 and P24; WR; Output latch
  • Page 66 – Port output mode register 1
  • Page 69 – Registers Controlling Port Function; The following three types of registers control the ports.
  • Page 70 – Don’t care
  • Page 71 – RESET input sets P0M0 and POM1 to 00H.; POM0 selects the output mode for a port in 8-bit units.; POM1 selects the output mode for P25 or P26 in 1-bit units.
  • Page 72 – Port Function Operation; latch can be output from the pins of the port.; output buffer is off.
  • Page 73 – of system clock oscillator is used.; System clock oscillator; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 5-1. Configuration of Clock Generator; Item; Figure 5-1. Block Diagram of Clock Generator
  • Page 74 – CHAPTER 5 CLOCK GENERATOR; Register Controlling Clock Generator; The clock generator is controlled by the following register.; Figure 5-2. Format of Processor Clock Control Register; PCC; : system clock oscillation frequency
  • Page 75 – System Clock Oscillators; Figure 5-3. External Circuit of System Clock Oscillator; OPEN
  • Page 76 – Examples of incorrect resonator connection; Figure 5-4 shows examples of incorrect resonator connection.; PORTn; (c) Wiring near high fluctuating current; (d) Current flowing through ground line of oscillator
  • Page 77 – Clock Generator Operation; System clock f; Clock to peripheral hardware
  • Page 78 – Changing Setting of CPU Clock; Time required for switching CPU clock; is used for the duration of several instructions after that (see; Table 5-2. Maximum Time Required for Switching CPU Clock; The following figure illustrates how the CPU clock switches.; which oscillation stabilization (2; operation can be selected.
  • Page 79 – CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01
  • Page 80 – A square wave of arbitrary frequency can be output.
  • Page 81 – RESET input sets CR0n undefined.; This is an 8-bit register used to count pulses.
  • Page 82 – Registers Controlling 8-Bit Timer/Event Counters 00 and 01; -bit timer mode control registers 00 and 01 (TMC00 and TMC01); : System clock oscillation frequency
  • Page 83 – TMC01 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 84 – PM2 is set by a 1-bit or 8-bit memory manipulation instruction.; Figure 6-5. Format of Port Mode Register 2; Symbol
  • Page 85 – and
  • Page 86 – Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00; t where N = 00H to FFH
  • Page 87 – TI01 pin input
  • Page 88 – ) and enable output of TO01 by setting; Minimum Pulse Width
  • Page 90 – Count pulse; Figure 6-11. Timing of External Event Counter Operation
  • Page 91 – Inadvertent Loop
  • Page 92 – CHAPTER 7 WATCHDOG TIMER; Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 7-3. Configuration of Watchdog Timer
  • Page 93 – Registers Controlling Watchdog Timer; This register sets the watchdog timer count clock.; Figure 7-2. Format of Timer Clock Select Register 2
  • Page 94 – RESET input sets the WDTM to 00H.; Figure 7-3. Format of Watchdog Timer Mode Register; started, it cannot be stopped by any means other than RESET input.; Cautions
  • Page 95 – Watchdog Timer Operation; Inadvertent Loop Detection Time
  • Page 96 – intervals specified by a count value set in advance.; Interval Time
  • Page 97 – CHAPTER 8 USB FUNCTION
  • Page 98 – USB Function Features; The features of the on-chip USB function provided for the; USB Function Configuration; The USB function consists of the following hardware.; Table 8-1. Configuration of USB Function
  • Page 99 – Figure 8-2. Block Diagram of USB Function; See
  • Page 100 – System clock oscillation frequency
  • Page 101 – bank switching ID detection buffer operation
  • Page 102 – USBRTP is read with an 8-bit memory manipulation instruction.; Figure 8-4. Configuration of Receive Token Bank; USBPOW address
  • Page 103 – USBRD is read with an 8-bit memory manipulation instruction.; Figure 8-5. Configuration of Receive Data Bank; The operation during reception appears as follows.
  • Page 104 – RESET input makes both USBTD0 and USBTD1 undefined.
  • Page 105 – USBPO; The operation during transmission appears as follows.
  • Page 107 – 0H must be set by software when an USB reset is received.; Figure 8-8. Configuration of TIDCMP and ADRCMP
  • Page 109 – Registers Controlling USB Function; Figure 8-10. Format of USB Receiver Enable Register
  • Page 110 – Figure 8-11. Format of Data/Handshake Packet Receive Mode Register; immediately when returning from the bus suspend mode.
  • Page 111 – This register indicates the receive status of each packet.
  • Page 112 – Figure 8-12. Format of Packet Receive Status Register; Bits 0 to 2: read only
  • Page 114 – Figure 8-14. Format of Token Packet Receive Result Store Register; If SETRX is set to 1, the following occurs.
  • Page 117 – (a) Transmit reservation for Endpoint 0 and IN token packet
  • Page 118 – (b) Transmit reservation for Endpoint1 and IN token packet
  • Page 121 – REMWUP is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 8-19. Format of Remote Wakeup Control Register
  • Page 122 – USB Function Operation; inadvertent program loop detection of the USB clock.
  • Page 124 – INTUSBTM occurred
  • Page 125 – Figure 8-21. Flow Chart of Remote Wakeup Control Operation; Bit 2 of remote wakeup control register (REMWUP)
  • Page 126 – Figure 8-22. Configuration of Remote Wakeup Control; TXEN; SEP, SEM disable signal
  • Page 127 – Interrupt Request from USB Function; Table 8-4. List of Sources of Interrupts from USB Function
  • Page 128 – This is an interrupt to release the STOP mode.; Figure 8-24. Timing of INTUSBRE Generation; INTUSBRE
  • Page 130 – USB Function Control; Relationship between packets and operation modes
  • Page 132 – counting during this period.
  • Page 136 – (1) USB token packet reception interrupt servicing
  • Page 138 – INTUSBTM occurrence
  • Page 140 – USB Function Internal Circuit Operations; TBYER: Bit 5 of token packet receive result store register (TRXRSL)
  • Page 142 – Data/handshake packet receive byte number counter
  • Page 144 – DTXCO0, DTXCO1: Data packet transmit byte number counter
  • Page 147 – Receive bank switching ID detection buffer operation; Bit 0 of packet receive status register (RXSTAT)
  • Page 148 – Figure 8-27. Timing of Sync Detection/USBCLK Detector Operation; The USB clock starts operating at the falling edge of f
  • Page 149 – Sync detection
  • Page 150 – This circuit performs NRZI encoding of data to be transmitted.; Figure 8-30. Timing of NRZI Encoder Operation; Figure 8-31. Flow Chart of NRZI Encoder Operation
  • Page 151 – “logic 0” simultaneously with the increment disable signal.; Figure 8-32. Timing of Bit Stuffing/Strip Controller Operation
  • Page 152 – Figure 8-33. Flow Chart of Bit Stuffing Control Operation
  • Page 153 – Figure 8-34. Flow Chart of Bit Strip Control Operation
  • Page 154 – Serial interface 10 has the following two modes.
  • Page 155 – CHAPTER 9 SERIAL INTERFACE 10; Configuration of Serial Interface 10; Serial interface 10 consists of the following hardware.; Table 9-1. Configuration of Serial Interface 10; synchronization with the serial clock.
  • Page 156 – Figure 9-1. Block Diagram of Serial Interface 10
  • Page 157 – Register Controlling Serial Interface 10; The following register is used to control serial interface 10.; Figure 9-2. Format of Serial Operation Mode Register 10
  • Page 158 – Table 9-2. Operating Mode Settings of Serial Interface 10; Can be used as port function.
  • Page 159 – Operation of Serial Interface 10; Serial interface 10 provides the following two modes.; Serial operation mode register 10 (CSIM10); CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 161 – End of transfer; two conditions are satisfied.
  • Page 162 – CHAPTER 10 REGULATOR; Supports power-saving mode, reducing power consumption in mode.; Figure 10-1. Block Diagram of Regulator and USB Driver/Receiver; voltage, connect the REGC pin to V
  • Page 163 – The following two types of interrupt functions are used.; Interrupt Sources and Configuration
  • Page 164 – CHAPTER 11 INTERRUPT FUNCTIONS; is the highest priority and 10 is the lowest.
  • Page 165 – Figure 11-1. Basic Configuration of Interrupt Function
  • Page 166 – Registers Controlling Interrupt Function; Interrupt request flag registers 0 and 1 (IF0 and IF1); Table 11-2. Flags Corresponding to Interrupt Request Signals
  • Page 167 – RESET input sets IF0 and IF1 to 00H.; Figure 11-2. Format of Interrupt Request Flag Register
  • Page 168 – RESET input sets MK0 and MK1 to FFH.; Figure 11-3. Format of Interrupt Mask Flag Register; This register is used to set the valid edge of INTP0.; Figure 11-4. Format of External Interrupt Mode Register 0
  • Page 169 – Figure 11-5. Configuration of Program Status Word
  • Page 170 – KRM00 is set with a 1-bit an 8-bit memory manipulation instruction.; Figure 11-6. Format of Key Return Mode Register 00; Register that selects the pin used for falling edge input.
  • Page 171 – Interrupt Servicing Operation
  • Page 172 – WDTM: Watchdog timer mode register
  • Page 173 – Maskable interrupt acknowledgment operation; from the one assigned the highest priority.; Figure 11-11. Interrupt Acknowledgment Program Algorithm
  • Page 174 – Figure 11-13. Timing of Interrupt Request Acknowledgment
  • Page 176 – Figure 11-14. Example of Multiplexed Interrupt Servicing; acknowledged after INTxx servicing is completed.
  • Page 177 – instructions include:
  • Page 178 – or for intermittent operations.
  • Page 179 – CHAPTER 12 STANDBY FUNCTION; Register controlling standby function; OSTS is set with an 8-bit memory manipulation instruction.
  • Page 180 – Standby Function Operation; The HALT mode is set by executing the HALT instruction.
  • Page 181 – (a) Releasing by unmasked interrupt request
  • Page 182 – Figure 12-3. Releasing HALT Mode by RESET Input; Table 12-2. Operation After Release of HALT Mode
  • Page 183 – The STOP mode is set by executing the STOP instruction.; Operation is enabled only when TI01 is selected as the count clock.
  • Page 184 – The STOP mode can be released by the following two sources.; mode is acknowledged.
  • Page 185 – Figure 12-5. Releasing STOP Mode by RESET Input
  • Page 186 – CHAPTER 13 RESET FUNCTION; oscillation stabilization time just after reset release.; s or more to the RESET pin.
  • Page 187 – Figure 13-2. Reset Timing by RESET Input
  • Page 188 – statuses become undefined.
  • Page 190 – CHAPTER 16 ELECTRICAL SPECIFICATIONS
  • Page 191 – CHAPTER 14; Flash Memory Characteristics; Programming using flash memory has the following advantages.; USB is supported by Flashpro IV only.; Figure 14-1. Environment for Writing Program to Flash Memory; Host machine
  • Page 192 – ELECTRICAL SPECIFICATIONS
  • Page 193 – voltage before starting programming.
  • Page 194 – Pin Connection List; voltage must be supplied before programming is started.; Pin must be connected.
  • Page 195 – Pin Connection Example; Connection pin of dedicated flash programmer; Serial Interface
  • Page 196 – Signal conflict; device or set the other device to the output high impedance status.; Abnormal operation of other device; input signals to the other device are ignored.; Figure 14-6. Abnormal Operation of Other Device
  • Page 198 – Connection of adapter for flash writing
  • Page 200 – CHAPTER 15 INSTRUCTION SET; Operand identifiers and description methods
  • Page 201 – Description of “flag operation” column
  • Page 202 – One instruction clock cycle is one CPU clock cycle (f; ) selected by the processor clock control
  • Page 207 – Instructions Listed by Addressing Type
  • Page 210 – CHAPTER 16 ELECTRICAL SPECIFICATIONS; Absolute Maximum Ratings (T
  • Page 211 – Indicates only oscillator characteristics. Refer to
  • Page 212 – DC Characteristics (T; RL is the resistance connected to the bus line.
  • Page 214 – AC Characteristics; CL is the capacitance of the USBDM and USBDP output lines.
  • Page 215 – Bit 4 of serial operation mode register 10 (CSIM10); CL is the capacitance of the SO output line.
  • Page 216 – AC Timing Measurement Points (Except X1 Input and USB Function); Clock timing; TI Timing
  • Page 217 – Serial Transfer Timing; Transmission differential signal jitter; Next bit; USB reset width
  • Page 218 – unstable upon the start of oscillation.; Data Hold timing (STOP Mode Release by RESET )
  • Page 219 – CHAPTER 17 PACKAGE DRAWINGS; detail of lead end; NOTE
  • Page 220 – CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS; Semiconductor Device Mounting
  • Page 221 – APPENDIX A DEVELOPMENT TOOLS; Support of the PC98-NX series
  • Page 222 – C library source file is not included in the software package.
  • Page 223 – A.1 Software Package; Software package; in the part number differs depending on the OS used.; A.2 Language Processing Software
  • Page 224 – A.3 Control Software
  • Page 225 – The TGB-044SAP is a product made by TOKYO ELETECH CORPORATION.
  • Page 227 – A.7 Notes on Target System Design; Emulation board; Target system; TGB-044SAP is a product of TOKYO ELETECH CORPORATION.
  • Page 229 – APPENDIX B REGISTER INDEX
  • Page 233 – APPENDIX C REVISION HISTORY
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User’s Manual

µµµµ

PD789800

µµµµ

PD78F9801

µµµµ

PD789800 Subseries

8-Bit Single-Chip Microcontrollers

Printed in Japan

Document No. U12978EJ3V0UD00 (3rd edition)
Date Published February 2003 N CP (K)

1998, 2003

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Summary

Page 3 - NOTES FOR CMOS DEVICES; circuitry. Each unused pin should be connected to V; or GND with a resistor, if it is considered

User’s Manual U12978EJ3V0UD 3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricit...

Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .

User’s Manual U12978EJ3V0UD 4 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country.Diversion contrary to the law of that country is prohibited. T h e i n f o r m a t i o n i n t h i s d o c u m e n t i s c u r r...

Page 5 - Regional Information; Device availability

User’s Manual U12978EJ3V0UD 5 Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power ...

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