NEC PD78052(A) - Manual
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Table of Contents:
- Page 3 – NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
- Page 4 – The customer must judge the need for license:
- Page 6 – Regional Information; Device availability
- Page 7 – Major Revisions in This Edition; APPENDIX B DEVELOPMENT TOOL; The mark shows major revised points.
- Page 9 – PREFACE; Readers
- Page 12 – Differences between; Modes of serial interface channel 0; Legend
- Page 13 – Related Documents; versions. However, preliminary versions are not marked as such.; Related documents for
- Page 17 – AV
- Page 18 – CHAPTER 4; CHAPTER 5
- Page 21 – Cautions on use of I
- Page 23 – APPENDIX A DIFFERENCES BETWEEN
- Page 28 – Handling of AV
- Page 37 – Notes
- Page 38 – CHAPTER 1 OUTLINE (; Ordering Information; Note; Under development; Caution The; indicates ROM code suffix.
- Page 39 – and require high reliability.
- Page 40 – Cautions 1. Be sure to connect IC (Internally Connected) pin to V; pin to V; Remark; Pin connection in parentheses is intended for the
- Page 41 – Pin Identifications
- Page 43 – Planned
- Page 45 – Pin connection in parentheses is intended for the
- Page 46 – Outline of Function; PD78P054 is the PROM version for the
- Page 48 – The mask ROM versions (; Table 1-2. Mask Options of Mask ROM Versions
- Page 50 – CHAPTER 2 OUTLINE (; Ordering Information
- Page 53 – : Connect individually to V; : Programming Power Supply
- Page 55 – Major differences among Y subseries are tabulated below.
- Page 57 – Outline of Function
- Page 58 – Table 2-1. Mask Options of Mask ROM Versions
- Page 60 – CHAPTER 3 PIN FUNCTION (
- Page 64 – Description of Pin Functions
- Page 66 – Serial interface automatic transmit/receive busy input pins; Caution; output and buzzer output.
- Page 68 – The following operating modes can be specified in 1-bit units.; to the function the user requires.
- Page 69 – that are not used as analog outputs must be set as follows:
- Page 70 – IC
- Page 76 – CHAPTER 4 PIN FUNCTION (
- Page 80 – Description of Pin Functions
- Page 83 – Port 5 can drive LEDs directly.
- Page 91 – CHAPTER 5 CPU ARCHITECTURE; Each product of the
- Page 92 – CHAPTER 5 CPU ARCHITECTURE
- Page 99 – The internal program memory space
- Page 100 – The; Part Number; The internal high-speed RAM can also be used as a stack memory.; Caution Do not access addresses where the SFR is not assigned.
- Page 101 – and general registers. This area is between FD00H and FFFFH for the
- Page 107 – memory size switching register.
- Page 109 – IE; Processor Registers; Figure 5-17. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 5-18. Program Status Word Configuration; acknowledged, and set to 1 when the EI instruction is executed.
- Page 110 – instruction execution.
- Page 111 – Figure 5-19. Stack Pointer Configuration
- Page 112 – processing and a register for interruption for each bank.
- Page 113 – Figure 5-22. General Register Configuration; FEFFH
- Page 116 – This register is provided only in the
- Page 118 – Instruction Address Addressing; of the next instruction.
- Page 119 – instruction branches to an area of addresses 0800H through 0FFFH.; In the case of CALLF !addr11 instruction
- Page 121 – Operand Address Addressing; manipulation during instruction execution.
- Page 122 – Identifier
- Page 123 – Operation code; Memory
- Page 127 – can be carried out for all the memory spaces.
- Page 129 – CHAPTER 6 PORT FUNCTIONS
- Page 130 – CHAPTER 6 PORT FUNCTIONS
- Page 134 – Port Configuration; A port consists of the following hardware:; connection for subsystem clock oscillation.; the output mode is used, set the interrupt mask flag to 1.
- Page 135 – Internal bus; PM
- Page 137 – Format and Figure 18-3 Serial Operating Mode Register 1 Format.
- Page 139 – 8-3 Serial Operating Mode Register 1 Format.
- Page 142 – KRMK; Figure 6-11. Block Diagram of Falling Edge Detection Circuit
- Page 144 – Pins P60 to P63 can drive LEDs directly.; depending on the following conditions:
- Page 150 – Port Function Control Registers; The following four types of registers control the ports.
- Page 153 – RESET input sets this register to 00H.; Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
- Page 154 – This register is used to set input/output of port 4.; Figure 6-21. Memory Expansion Mode Register Format
- Page 155 – KRM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-22. Key Return Mode Register Format
- Page 156 – Port Function Operations
- Page 157 – latch contents are output from the pins.; than the manipulated bit.; Selection of Mask Option; Table 6-6. Comparison between Mask ROM Version and PROM Version; Pin Name
- Page 159 – types of system clock oscillators are available.; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 7-1. Clock Generator Configuration
- Page 160 – CHAPTER 7 CLOCK GENERATOR; Figure 7-1. Block Diagram of Clock Generator
- Page 161 – FRC; Clock Generator Control Register; The clock generator is controlled by the following two registers:; Figure 7-2. Subsystem Clock Feedback Resistor
- Page 162 – Figure 7-3. Processor Clock Control Register Format; system clock oscillation. A STOP instruction should not be used.; Caution Bit 3 must be set to 0.; or f; : Subsystem clock oscillator frequency
- Page 163 – The fastest instruction of the; ) and the minimum instruction execution time are as shown in; : Main system clock oscillation frequency; : Subsystem clock oscillation frequency
- Page 164 – OSMS is set with 8-bit memory manipulation instruction.; Figure 7-4. Oscillation Mode Selection Register Format; Remarks f
- Page 165 – System Clock Oscillator; connected to the X1 and X2 pins.; Figure 7-6. External Circuit of Main System Clock Oscillator
- Page 166 – and an antiphase clock signal to the XT2 pin.; PORTn
- Page 167 – (d) Current flows through the grounding line; in series on the XT2 side.; between XT2 and X1 directly to V
- Page 168 – The scaler divides the main system clock oscillator output (f; connect the XT1 and XT2 pins as follows.; pins as described above.
- Page 169 – Clock Generator Operations
- Page 170 – (b) Operation when MCC is set in case of main system clock operation
- Page 171 – the following operations are carried out.; Changing System Clock and CPU Clock Settings
- Page 172 – Table 7-3. Maximum Time Required for CPU Clock Switchover; MCS: Oscillation mode selection register bit 0
- Page 173 – System clock and CPU clock switching procedure
- Page 175 – Outline of Timers Incorporated in the; Subseries and related circuits are outlined below.
- Page 177 – Values in parentheses when operated at f
- Page 179 – The 16-bit timer/event counter consists of the following hardware.; Refer to Figure 21-1. Basic Configuration of Interrupt Function.; Notes 1. Edge detection circuit
- Page 181 – one pulse cannot be counted.; CR01 is set with a 16-bit memory manipulation instruction.
- Page 184 – : Subsystem clock oscillation frequency; Figures in parentheses apply to operation with f; TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 185 – When using the PWM mode, set the PWM mode and then set data to CR00.
- Page 186 – Cautions 1. Timer operation must be stopped before setting CRC0.; TOC0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 187 – If LVS0 and LVR0 are read after data is set, they will be 0.
- Page 188 – PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 189 – Figure 8-8. External Interrupt Mode Register 0 Format
- Page 190 – SCS is set with an 8-bit memory manipulation instruction.
- Page 191 – the description of the respective control registers for details.; Clear & start on match TM0 and CR00
- Page 192 – Clear Circuit; Figure 8-11. Interval Timer Configuration Diagram
- Page 193 – : Main system clock oscillation frequency; Figures in parentheses apply to operation with f; and the sub-cycle determined by 2; Be sure to write 0 to bits 0 and 1 of CR00.
- Page 194 – PWM mode; Figure 8-13. Control Register Settings for PWM Output Operation
- Page 195 – Switching Circuit; The analog output voltage (V; : External switching circuit reference voltage; Figure 8-14. Example of D/A Converter Configuration with PWM Output; synthesizer type TV tuner.; Figure 8-15. TV Tuner Application Circuit Example
- Page 196 – Figure 8-16. Control Register Settings for PPG Output Operation
- Page 197 – Pulse width measurement operations; eliminating noise with a short pulse width.; Free-Running Counter and One Capture Register
- Page 198 – Count Clock; and One Capture Register (with Both Edges Specified)
- Page 199 – (2) Measurement of two pulse widths with free-running counter; thus eliminating noise with a short pulse width.
- Page 200 – Figure 8-21. Timing of Pulse Width Measurement Operation with
- Page 201 – Free-Running Counter and Two Capture Registers
- Page 202 – Counter and Two Capture Registers (with Rising Edge Specified)
- Page 203 – (4) Pulse width measurement by means of restart; with a short pulse width.; compare register 00 (CR00) cannot perform the capture operation.
- Page 205 – Figure 8-27. External Event Counter Configuration Diagram
- Page 206 – frequency to be output.; Figure 8-29. Control Register Settings in Square-Wave Output Mode
- Page 210 – Clear & start with valid edge of TI00/P00 pin; P30 pin with a TI00/P00 valid edge as an external trigger.
- Page 213 – (4) Capture register data retention timings; detection of the valid edge.; Figure 8-37. Capture Register Data Retention Timing
- Page 214 – OFV0 flag is set to 1 in the following case.; Figure 8-38. Operation Timing of OVF0 Flag
- Page 215 – CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; • Interval timer
- Page 216 – CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; Interrupt requests are generated at the preset time intervals.
- Page 218 – Interrupt requests can be generated at the preset time intervals.
- Page 219 – Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
- Page 222 – The section in the broken line is an output control circuit.; : Serial clock frequency; INV
- Page 224 – Figure 9-4. Timer Clock Select Register 1 Format; Figures in parentheses apply to operation with f
- Page 225 – TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 226 – timer registers 1 and 2.; Cautions 1. Be sure to set TOC1 after stopping timer operation.
- Page 228 – Figure 9-8. Interval Timer Operation Timings
- Page 229 – Values in parentheses when operated at f
- Page 231 – is input. Either the rising or falling edge can be selected.; TI1 Pin Input
- Page 232 – a square wave with any selected frequency to be output.
- Page 234 – the overflow signal of TM1 becomes the count clock of TM2.; Figure 9-11. Interval Timer Operation Timing
- Page 236 – falling edge can be selected.
- Page 238 – with the count pulse.; Count Pulse
- Page 239 – Figure 9-15. Event Counter Operation Timing; is necessary to restart the timer after changing CR10 and CR20.; Interrupt Request Flag
- Page 242 – CHAPTER 10 WATCH TIMER; Watch Timer Configuration
- Page 243 – Prescaler; Clear
- Page 244 – Figure 10-2. Timer Clock Select Register 2 Format
- Page 245 – RESET input sets TMC2 to 00H.; Figure 10-3. Watch Timer Mode Control Register Format
- Page 246 – Watch Timer Operations; Table 10-3. Interval Timer Interval Time
- Page 248 – CHAPTER 11 WATCHDOG TIMER; MCS : Oscillation mode selection register bit 0
- Page 249 – Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 11-3. Watchdog Timer Configuration; Item; Figure 11-1. Watchdog Timer Block Diagram; Control register
- Page 250 – Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
- Page 251 – Figure 11-2. Timer Clock Select Register 2 Format
- Page 252 – WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 11-3. Watchdog Timer Mode Register Format
- Page 253 – Watchdog Timer Operations; Table 11-4. Watchdog Timer Runaway Detection Times
- Page 254 – requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time; Figures in parentheses apply to operation with f
- Page 255 – CLOE; CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Follow the procedure below to output clock pulses.
- Page 256 – CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Clock Output Control Circuit Configuration; Table 12-1. Clock Output Control Circuit Configuration; Figure 12-2. Clock Output Control Circuit Block Diagram
- Page 257 – Clock Output Function Control Registers; This register sets PCL output clock.
- Page 258 – Figure 12-3. Timer Clock Select Register 0 Format
- Page 259 – Figure 12-4. Port Mode Register 3 Format
- Page 261 – CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 13-1. Buzzer Output Control Circuit Configuration; Figure 13-1. Buzzer Output Control Circuit Block Diagram
- Page 262 – CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Buzzer Output Function Control Registers; This register sets the buzzer output frequency.; watchdog timer count clock.
- Page 263 – Figure 13-2. Timer Clock Select Register 2 Format
- Page 264 – Figure 13-3. Port Mode Register 3 Format
- Page 265 – CHAPTER 14 A/D CONVERTER
- Page 266 – CHAPTER 14 A/D CONVERTER; Tap Selector; Bits 0 and 1 of external interrupt mode register 1 (INTM1)
- Page 267 – ADCR is read with an 8-bit memory manipulation instruction.; and generates a voltage to be compared; or lower than AV; converted values of other channels.
- Page 269 – • External interrupt mode register 1 (INTM1)
- Page 270 – Setting prohibited because A/D conversion time is less than 19.1
- Page 271 – ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
- Page 272 – This register sets the valid edge for INTP3 to INTP6.; Figure 14-5. External Interrupt Mode Register 1 Format
- Page 273 – , the MSB of SAR remains set. If the input
- Page 274 – After RESET input, the value of ADCR is undefined.
- Page 275 – Input voltage and conversion results
- Page 276 – The following two ways are available to start A/D conversion.
- Page 277 – continues repeatedly until new data is written to ADM.
- Page 278 – pin at this time, this current must
- Page 279 – Figure 14-11. Analog Input Pin Disposition
- Page 280 – pin; The AV; Therefore, be sure to apply the same voltage as V; to this pin even when the application circuit is designed; Pin
- Page 281 – CHAPTER 15 D/A CONVERTER; The conversion method used is the R-2R resistor ladder method.
- Page 282 – CHAPTER 15 D/A CONVERTER; The D/A converter consists of the following hardware.
- Page 283 – RESET input sets these registers to 00H.; trigger and before the next output trigger.; DACSn
- Page 284 – The DAM is set with a 1-bit or 8-bit memory manipulation instruction.; a pull-up resistor should be disconnected.
- Page 285 – with the output triggers.
- Page 286 – Figure 15-3. Use Example of Buffer Amplifier; When only either one of the D/A converter channels is used with AV; , the other pins that are not used; low level from the pin.
- Page 287 – CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
- Page 288 – CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions
- Page 289 – more devices can be used as input/output ports.; Master CPU
- Page 290 – Serial Interface Channel 0 Configuration; Table 16-2. Serial Interface Channel 0 Configuration
- Page 291 – Figure 16-2. Serial Interface Channel 0 Block Diagram
- Page 292 – SIO0 is set with an 8-bit memory manipulation instruction.
- Page 293 – is used, the circuit also controls clock output to the SCK0/P27 pin.
- Page 294 – Serial Interface Channel 0 Control Registers
- Page 295 – Figure 16-3. Timer Clock Select Register 3 Format
- Page 296 – function and displays the address comparator match signal.
- Page 297 – ) the operation of serial interface channel
- Page 298 – SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 300 – SINT is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 16-6. Interrupt Timing Specify Register Format; SVA
- Page 301 – Serial Interface Channel 0 Operations; • Operation stop mode
- Page 302 – CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 305 – SI0 pin is latched in SIO0 at the rising edge of SCK0.; RELT
- Page 306 – Figure 16-9. Circuit of Switching in Transfer Bit Order; conditions are satisfied.
- Page 307 – the board can be decreased.; Figure 16-10. Example of Serial Bus Configuration with SBI
- Page 308 – software, the software must be heavily loaded.; (b) Chip select function by address transmission; The busy signal to report the slave busy state is controlled.
- Page 309 – The dotted line indicates READY status.; Address Transfer
- Page 310 – This signal is output by the master device.
- Page 311 – in order to select a particular slave device.; Figure 16-15. Slave Selection with Address
- Page 312 – by address transmission.; Data
- Page 313 – [When output in synchronization with 11th clock SCK0]
- Page 314 – terminates the output of SCK0 serial clock.
- Page 320 – ACKT
- Page 321 – (b) When set after completion of transfer; ACKE
- Page 322 – (a) When ACK signal is output at 9th clock of SCK0
- Page 324 – In BUSY state, transfer starts after the READY state is set.
- Page 326 – of using the address match detection method.; two or more devices by outputting an “address” to the serial bus.
- Page 329 – Figure 16-29. Data Transmission from Master Device to Slave Device
- Page 330 – Figure 16-30. Data Transmission from Slave Device to Master Device
- Page 331 – write FFH to SIO0 in advance.; before the first byte of serial transmission.
- Page 332 – transfer of the 1st byte after RESET input.
- Page 333 – Master
- Page 336 – CSIIF0 : Interrupt request flag corresponding to INTCSI0
- Page 337 – is carried out bit-wise in synchronization with the serial clock.
- Page 338 – Figure 16-33 shows RELT and CMDT operations.
- Page 339 – normal serial clock output.
- Page 341 – CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
- Page 342 – CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions; Serial interface channel 0 employs the following four modes.; transfer processing time.
- Page 343 – This mode is in compliance with the I; Figure 17-1. Serial Bus Configuration Example Using I
- Page 344 – Serial Interface Channel 0 Configuration; Table 17-2. Serial Interface Channel 0 Configuration
- Page 345 – Figure 17-2. Serial Interface Channel 0 Block Diagram
- Page 348 – Serial Interface Channel 0 Control Registers
- Page 349 – Figure 17-3. Timer Clock Select Register 3 Format
- Page 351 – Figure 17-4. Serial Operating Mode Register 0 Format; C bus mode, the clock frequency becomes 1/16 of that output from TO2.
- Page 353 – Notes 1. Setting should be performed before transfer.; However, the BSYE flag is not cleared to 0.; Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
- Page 354 – RESET input sets SINT to 00H.; When not using the I
- Page 355 – Notes 1. When using wake-up function in the I
- Page 356 – Serial Interface Channel 0 Operations
- Page 360 – Figure 17-9. Circuit of Switching in Transfer Bit Order
- Page 366 – Figure 17-12 shows RELT and CMDT operations.
- Page 367 – C bus mode operation; The I; Figure 17-13. Example of Serial Bus Configuration Using I
- Page 368 – C bus mode functions
- Page 369 – is the slave device which will send data to the master.; Figure 17-17. Transfer Direction Specification; Transfer direction
- Page 370 – the master device outputs no acknowledge signal in this case.
- Page 371 – to preparing for transmitting or receiving data.
- Page 373 – SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
- Page 374 – Notes 1. This setting must be performed prior to transfer start.
- Page 375 – SINT is set by the 1-bit or 8-bit memory manipulation instruction.
- Page 376 – A list of signals in the I; C Bus Mode
- Page 377 – In the I
- Page 378 – (a) Comparison of SIO0 data before and after transmission
- Page 379 – Figure 17-22. Data Transmission from Master to Slave
- Page 382 – Figure 17-23. Data Transmission from Slave to Master
- Page 385 – C bus mode
- Page 386 – output latch to 1 after execution of an SIO0 write instruction.
- Page 390 – To internal logic
- Page 391 – Figure 17-29. Logic Circuit of SCL Signal
- Page 393 – Serial interface channel 1 employs the following three modes.
- Page 394 – CHAPTER 18 SERIAL INTERFACE CHANNEL 1; Serial Interface Channel 1 Configuration; Table 18-1. Serial Interface Channel 1 Configuration
- Page 395 – Figure 18-1. Serial Interface Channel 1 Block Diagram
- Page 396 – SIO1 is set with an 8-bit memory manipulation instruction.; RESET input sets ADTP to 00H.
- Page 397 – Serial Interface Channel 1 Control Registers; • Serial operating mode register 1 (CSIM1)
- Page 398 – Figure 18-2. Timer Clock Select Register 3 Format
- Page 399 – CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 18-3. Serial Operation Mode Register 1 Format
- Page 400 – execution and error detection.
- Page 401 – Notes 1. The interval is dependent only on CPU processing.
- Page 402 – , the minimum interval time
- Page 405 – Serial Interface Channel 1 Operations; Notes 1. Can be used freely as port function.
- Page 407 – pin is latched into SIO1 at the rising edge of SCK1.
- Page 408 – Figure 18-7. Circuit of Switching in Transfer Bit Order
- Page 411 – ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 412 – Main system clock frequency (f
- Page 416 – subtracting 1 from the number of transmit data bytes.
- Page 417 – transmitted or received.; Figure 18-8. Basic Transmission/Reception Mode Operation Timings; CSIIF1 : Interrupt request flag; TRF
- Page 418 – ADTP : Automatic data transmit/receive address pointer
- Page 419 – is transferred from the buffer RAM to SIO1.; FADFH
- Page 421 – BUSY pins can be used as normal input/ports.; Figure 18-11. Basic Transmission Mode Operation Timings
- Page 422 – Figure 18-12. Basic Transmission Mode Flowchart; ADTP : Automatic data transmit/receive address pointer
- Page 423 – Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
- Page 425 – are transmitted again.; Figure 18-14. Repeat Transmission Mode Operation Timing; Interval
- Page 426 – Figure 18-15. Repeat Transmission Mode Flowchart
- Page 428 – (b) Upon completion of transmission of 6 bytes
- Page 429 – is suspended upon completion of 8-bit data transfer.
- Page 430 – device and slave device.; Master Device
- Page 431 – The busy signal cannot be controlled with an external clock.; CSIIF1: Interrupt request flag
- Page 432 – or receiving can wait while the busy signal is being input.
- Page 434 – (c) Bit Slippage Detection Function Through the Busy Signal; bit slippage can be detected.; CSIIF1 : Interrupt Request Flag
- Page 435 – interval may be longer than the value indicated by paragraph (b).; CSIIF1: Interrupt request flag
- Page 439 – Serial interface channel 2 has the following three modes.
- Page 440 – CHAPTER 19 SERIAL INTERFACE CHANNEL 2; Serial Interface Channel 2 Configuration; Table 19-1. Serial Interface Channel 2 Configuration
- Page 441 – Figure 19-1. Serial Interface Channel 2 Block Diagram; See Figure 19-2 for the baud rate generator configuration.
- Page 442 – Figure 19-2. Baud Rate Generator Block Diagram
- Page 443 – Writing data to TXS starts the transmit operation.; RXS cannot be directly manipulated by a program.
- Page 444 – Serial Interface Channel 2 Control Registers; Figure 19-3. Serial Operating Mode Register 2 Format
- Page 445 – ASIM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 19-4. Asynchronous Serial Interface Mode Register Format
- Page 446 – Table 19-2. Serial Interface Channel 2 Operating Mode Settings; TXE RXE SCK CSIE2 CSIM22 CSCK
- Page 447 – will continue to be generated until RXB is read.
- Page 448 – BRGC is set with an 8-bit memory manipulation instruction.; Baud Rate Generator Input Clock Selection
- Page 450 – scaled from the clock input from the ASCK pin.; Table 19-3. Relation between Main System Clock and Baud Rate; MCS: Oscillation mode selection register bit 0
- Page 451 – Frequency of clock input to ASCK pin
- Page 452 – Serial Interface Channel 2 Operation
- Page 454 – CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 456 – ASIS is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 459 – a signal scaled from the clock input from the ASCK pin.; Table 19-5. Relation between Main System Clock and Baud Rate
- Page 461 – One data frame consists of the following bits.; Stop Bit
- Page 462 – Even parity
- Page 463 – Interrupt Request Generation Timing
- Page 464 – start bit, reception of one frame of data ends.; Figure 19-9. Asynchronous Serial Interface Reception Completion
- Page 466 – FFH, then set the TXE to 1 before executing the next transmission.; The State of Receive Buffer Register (RXB) and Whether
- Page 472 – received bit by bit in synchronization with the serial clock.; SRIF
- Page 473 – Figure 19-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
- Page 474 – Limitations when UART mode is used; ISRM : Bit 1 of asynchronous serial interface mode register (ASIM); : Source clock of 5-bit counter of baud rate generator; Countermeasures
- Page 475 – • In case of parity error; Example of preventive measures; Here is an example of the above preventive measures.
- Page 477 – CHAPTER 20 REAL-TIME OUTPUT PORT
- Page 478 – CHAPTER 20 REAL-TIME OUTPUT PORT; Real-Time Output Port Configuration; The real-time output port consists of the following hardware.
- Page 480 – Real-Time Output Port Control Registers; The following three registers control the real-time output port.; Figure 20-3. Port Mode Register 12 Format; RTPM is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 481 – Table 20-3. Real-time Output Port Operating Mode and Output Trigger
- Page 483 – The following three types of interrupt functions are used.
- Page 484 – CHAPTER 21 INTERRUPT AND TEST FUNCTIONS; Interrupt Sources and Configuration; is the highest priority and 20 is the lowest priority.
- Page 485 – is the highest priority and 18 is the lowest priority.
- Page 488 – Interrupt Function Control Registers; to interrupt request sources.
- Page 489 – or upon application of RESET input.; Figure 21-2. Interrupt Request Flag Register Format
- Page 490 – RESET input sets these registers to FFH.; Figure 21-3. Interrupt Mask Flag Register Format
- Page 491 – Set always 1 in PR1L bits 3 through 7.; Figure 21-4. Priority Specify Flag Register Format
- Page 492 – These registers set the valid edge for INTP0 to INTP6.; Figure 21-5. External Interrupt Mode Register 0 Format
- Page 493 – Figure 21-6. External Interrupt Mode Register 1 Format
- Page 495 – Sampling Clock; Sampling Clock
- Page 496 – processing are mapped.; Figure 21-9. Program Status Word Configuration
- Page 497 – Interrupt Servicing Operations; table contents are loaded into PC and branched.
- Page 498 – WDTM; Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing; : Watchdog timer interrupt request flag
- Page 499 – If a new non-maskable interrupt request is generated during; Main Routine
- Page 500 – Maskable interrupt request acknowledge operation
- Page 501 – Start
- Page 503 – Software interrupt request acknowledge operation; servicing, and set interrupt enable state.
- Page 504 – Example 1. A multiple interrupt is generated at twice
- Page 505 – after execution of one main processing instruction.
- Page 506 – CPU processing
- Page 507 – Figure 21-18. Basic Configuration of Test Function
- Page 508 – It indicates whether a watch timer overflow is detected or not.
- Page 509 – Figure 21-21. Key Return Mode Register Format; timer overflow cycle.
- Page 511 – Table 22-1. Pin Functions in External Memory Expansion Mode
- Page 512 – CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION; Memory map of
- Page 514 – when the
- Page 515 – less than 56 Kbytes by the memory size switching register (IMS).; Reserved
- Page 516 – External Device Expansion Function Control Register; RESET input sets this register to 10H.; Figure 22-2. Memory Expansion Mode Register Format
- Page 517 – Figure 22-3. Memory Size Switching Register Format
- Page 518 – External Device Expansion Function Timing; from external memory.
- Page 519 – Figure 22-4. Instruction Fetch from External Memory
- Page 520 – Figure 22-5. External Memory Read Timing
- Page 521 – Figure 22-6. External Memory Write Timing
- Page 522 – Figure 22-7. External Memory Read Modify Write Timing
- Page 523 – Example of Connection with Memory; This section provides
- Page 525 – intermittent operations such as in watch applications.; request, it enables intermittent operations to be carried out.; the main system clock or the subsystem clock.
- Page 526 – CHAPTER 23 STANDBY FUNCTION; Standby function control register; OSTS is set with an 8-bit memory manipulation instruction.; Values in parentheses apply to operating at f
- Page 527 – Standby Function Operations; The operating status in the HALT mode is described below.; Notes 1. Including when external clock is not supplied
- Page 528 – (a) Clear upon unmasked interrupt request; status is acknowledged.
- Page 529 – Figure 23-3. HALT Mode Release by RESET Input; : main system clock oscillation frequency; Table 23-2. Operation after HALT Mode Release
- Page 530 – via a pull-up resistor; The operating status in the STOP mode is described below.
- Page 531 – (a) Release by unmasked interrupt request
- Page 532 – Figure 23-5. Release by STOP Mode RESET Input; Table 23-4. Operation after STOP Mode Release
- Page 533 – CHAPTER 24 RESET FUNCTION; (2) Internal reset by watchdog timer overrun time detection; Cautions 1. For an external reset, input a low level for 10
- Page 534 – Figure 24-2. Timing of Reset Input by RESET Input
- Page 535 – CHAPTER 24 RESET FUNCTION; The values after reset depend on the product.
- Page 537 – CHAPTER 25 ROM CORRECTION; ROM Correction Configuration; Table 25-1. ROM Correction Configuration
- Page 538 – RESET input sets CORAD0 and CORAD1 to 0000H.; Figure 25-2. Correction Address Registers 0 and 1 Format
- Page 539 – ROM Correction Control Registers; RESET input sets CORCN to 00H.; Figure 25-3. Correction Control Register Format
- Page 540 – ROM Correction Application; EEPROM; EEPROM; FFH
- Page 541 – expansion RAM with the main program.
- Page 543 – Internal ROM; ROM Correction Example; address value after the main program is started.
- Page 544 – Program Execution Flow; Area filled with diagonal lines : Internal expansion RAM
- Page 545 – (2) Branches to branch destination judgment program
- Page 546 – Cautions on ROM Correction
- Page 549 – Table 26-3. Examples of Memory Size Switching Register Settings (; Relevant Mask ROM Version
- Page 550 – Table 26-4. Examples of Memory Size Switching Register Settings (
- Page 551 – Internal Expansion RAM Size Switching Register
- Page 552 – PROM Programming; Caution In case of the; Table 26-6. PROM Programming Operating Modes
- Page 554 – N = Last address of program; Figure 26-4. Page Program Mode Flowchart
- Page 556 – Figure 26-6. Byte Program Mode Flowchart
- Page 557 – Cautions 1. Be sure to apply V; before applying V; , and remove it after removing V; to the V; pin may have an adverse affect on device reliability.
- Page 558 – pin. Unused pins are handled as shown in paragraph,; and V; (3) Input the address of data to be read to pins A0 through A16.
- Page 559 – Screening of One-Time PROM Versions
- Page 561 – CHAPTER 27 INSTRUCTION SET; This chapter describes each instruction set of the
- Page 562 – CHAPTER 27 INSTRUCTION SET; Legends Used in Operation List; Operand identifiers and description methods
- Page 563 – Description of “operation” column
- Page 564 – When an area except the internal high-speed RAM area is accessed.; ) selected by the processor clock; This clock cycle applies to internal ROM program.; MOV
- Page 565 – ADD
- Page 566 – SUB
- Page 567 – OR
- Page 572 – Instructions Listed by Addressing Type
- Page 577 – Table A-1 shows the major differences between the
- Page 578 – APPENDIX A DIFFERENCES BETWEEN; PROM version only
- Page 579 – APPENDIX B DEVELOPMENT TOOLS; Figure B-1 shows the configuration of the development tools.
- Page 580 – APPENDIX B DEVELOPMENT TOOLS
- Page 582 – B.1 Language Processing Software
- Page 584 – B.2 PROM Writing Tools
- Page 586 – Notes 1. Under development
- Page 590 – I T E M
- Page 592 – I J J J; Note Product by TOKYO ELETECH CORPORATION.
-
Page 593 – APPENDIX C EMBEDDED SOFTWARE;
- Page 594 – APPENDIX C REGISTER INDEX
- Page 595 – APPENDIX D REGISTER INDEX
- Page 596 – APPENDIX D REGISTER INDEX
- Page 599 – APPENDIX E REVISION HISTORY; Major revisions by edition and revised chapters are shown below.
- Page 603 – Thank you for your kind support.; Document Rating; Name; Facsimile
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PD78054, 78054Y SUBSERIES
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PD78054
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PD78P054
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PD78055
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PD78056Y
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PD78056
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PD78054(A)
Document No. U11747EJ5V0UM00 (5th edition)
Date Published April 1998 N CP (K)
1992
User’s Manual
Printed in Japan
©
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Summary
Page 3 - NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and q...
Page 4 - The customer must judge the need for license:
4 FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. H...
Page 6 - Regional Information; Device availability
6 Regional Information Some information contained in this document may vary from country to country. Before using any NECproduct in your application, pIease contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will verify: • Device availability ...
