Page 3 - NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and q...
Page 4 - The customer must judge the need for license:
4 FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. H...
Page 6 - Regional Information; Device availability
6 Regional Information Some information contained in this document may vary from country to country. Before using any NECproduct in your application, pIease contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will verify: • Device availability ...
Page 7 - Major Revisions in This Edition; APPENDIX B DEVELOPMENT TOOL; The mark shows major revised points.
7 Major Revisions in This Edition Page Description Throughout Addition of µ PD78052(A),78053(A), 78054(A) to the applicable types Deletion of µ PD78P054Y from the applicable types Deletion of the following package from the µ PD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y Subseries: • 80-...
Page 9 - PREFACE; Readers
9 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78054 and 78054Y Subseries and design and develop its application systems and programs. The target products are the products of the following subseries. • µ PD78054 Subseries : µ PD7805...
Page 12 - Differences between; Modes of serial interface channel 0; Legend
12 Differences between µ PD78054 and µ PD78054Y Subseries: The µ PD78054 and µ PD78054Y Subseries are different in the following functions of the serial interface channel 0. Modes of serial interface channel 0 µ PD78054 µ PD78054Y Subseries Subseries 3-wire serial I/O mode √ √ 2-wire serial I/O mode...
Page 13 - Related Documents; versions. However, preliminary versions are not marked as such.; Related documents for
13 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for µ PD78054 Subseries Document name Document No. Japanese English µ PD78052, 78053, 78054, 78055, 78056, 78058 Data She...
Page 17 - AV
17 TABLE OF CONTENTS CHAPTER 1 GENERAL ( µ PD78054 Subseries) ............................................................................ 37 1.1 Features ............................................................................................................................. 37 1.2 Applications...
Page 18 - CHAPTER 4; CHAPTER 5
18 3.2.18 V DD ....................................................................................................................................... 70 3.2.19 V SS .........................................................................................................................................
Page 21 - Cautions on use of I
21 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .................................................................... 261 13.1 Buzzer Output Control Circuit Functions ............................................................................. 261 13.2 Buzzer Output Control Circuit Configuration ..........
Page 23 - APPENDIX A DIFFERENCES BETWEEN
23 23.2 Standby Function Operations .......................................................................................... 527 23.2.1 HALT mode .......................................................................................................................... 527 23.2.2 STOP mode ...........
Page 28 - Handling of AV
28 LIST OF FIGURES (4/8) Figure No. Title Page 12-1. Remote Controlled Output Application Example ........................................................................... 255 12-2. Clock Output Control Circuit Block Diagram ............................................................................
Page 37 - Notes
37 CHAPTER 1 GENERAL ( µ PD78054 Subseries) 1.1 Features On-chip high-capacity ROM and RAM Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS). 2. The capacity of internal high-speed RAM can be changed by means of t...
Page 38 - CHAPTER 1 OUTLINE (; Ordering Information; Note; Under development; Caution The; indicates ROM code suffix.
38 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.2 Applications µ PD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058: Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. µ PD78052(A), 78053(A), 78054(A): Control unit fo...
Page 39 - and require high reliability.
39 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.4 Quality Grade Part number Package Quality grade µ PD78052GC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µ PD78052GK- ××× -BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard µ PD78053GC- ××× -8BT 80-pin plastic QF...
Page 40 - Cautions 1. Be sure to connect IC (Internally Connected) pin to V; pin to V; Remark; Pin connection in parentheses is intended for the
40 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78P054GC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78052GC- ××× -8BT, 78053GC- ××× -8BT, 78054GC- ××× -8BT, 7...
Page 41 - Pin Identifications
41 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) Pin Identifications A8 to A15 : Address Bus P130, P131 : Port13 AD0 to AD7 : Address/Data Bus PCL : Programmable Clock ANI0 to ANI7 : Analog Input RD : Read Strobe ANO0, ANO1 : Analog Output RESET : Reset ASCK : Asynchronous Serial Clock RTP0 to RTP7 : Rea...
Page 43 - Planned
43 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Note Planned µ PD78098 80-pin Added IEBus controller to µ PD78054 µ PD78044F 80-pin Basic subseries for driving FIPs, 34 display outputs µ...
Page 45 - Pin connection in parentheses is intended for the
45 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P054, 78P058. 16-bit TIMER/EVENT COUNTER 8-bit TIMER/EVENT COUNTER 1 WATCHDOG TIMER WATCH TIMER SERIALINTERFA...
Page 46 - Outline of Function; PD78P054 is the PROM version for the
46 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.8 Outline of Function ROM Mask ROM PROM Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 3 Note 3 High-speed RAM 512 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes Note 3 Note 3 Buffer RAM 32 bytes Exp...
Page 48 - The mask ROM versions (; Table 1-2. Mask Options of Mask ROM Versions
48 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.9 Differences between Standard Quality Grade Products and (A) Products Table 1-1 shows the differences between the standard quality grade products ( µ PD78052, 78053, 78054) and (A) products ( µ PD78052(A), 78053(A), 78054(A)). Table 1-1. Differences bet...
Page 50 - CHAPTER 2 OUTLINE (; Ordering Information
50 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.2 Applications Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number Package Internal ROM µ PD78052YGC- ××× -8BT 80-pin plastic QFP (14 × 14 m...
Page 53 - : Connect individually to V; : Programming Power Supply
53 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78P058YGC-8BT • 80-pin ceramic WQFN (14 × 14 mm) µ PD78P058YKK-T Cautions 1. (L) : Connect individually to V SS via a pull-down resistor. 2. V SS : Connect to the gro...
Page 55 - Major differences among Y subseries are tabulated below.
55 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) Major differences among Y subseries are tabulated below. Function ROM Configuration of Serial Interface I/O V DD Subseries Capacity MIN. Control µ PD78078Y 48K to 60K 3-wire/2-wire/I 2 C : 1 ch 88 1.8 V 3-wire with automatic transmit/receive function : 1 ...
Page 57 - Outline of Function
57 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.8 Outline of Function ROM Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 512 bytes 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 6...
Page 58 - Table 2-1. Mask Options of Mask ROM Versions
58 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) Maskable Internal: 13 Vectored External: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.0 to 6.0 V Operating ambient temperature T A = –40 to +85 ° C Package • 80-pin plastic QFP (14 × 14 ...
Page 60 - CHAPTER 3 PIN FUNCTION (
60 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Input P40 to P47 Input AD0 to AD7 (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified in 1-bit units. T...
Page 64 - Description of Pin Functions
64 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger s...
Page 66 - Serial interface automatic transmit/receive busy input pins; Caution; output and buzzer output.
66 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the f...
Page 68 - The following operating modes can be specified in 1-bit units.; to the function the user requires.
68 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit unit...
Page 69 - that are not used as analog outputs must be set as follows:
69 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bi...
Page 70 - IC
70 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.13 AV DD Analog power supply pin of A/D converter. Always use the same voltage as that of the V DD pin even when A/D converter is not used. 3.2.14 AV SS This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage a...
Page 76 - CHAPTER 4 PIN FUNCTION (
76 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) P70 SI2/RxD P71 Input SO2/TxD P72 SCK2/ASCK Input P40 to P47 Input AD0 to AD7 N-ch open drain input/output port.On-chip pull-up resistor can bespecified by mask option.(Mask ROM version only).LEDs can be driven directly. (1) Port pins (2/3) Pin Name ...
Page 80 - Description of Pin Functions
80 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger ...
Page 83 - Port 5 can drive LEDs directly.
83 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode These p...
Page 91 - CHAPTER 5 CPU ARCHITECTURE; Each product of the
91 CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Each product of the µ PD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1 to 5-8 show memory maps. Figure 5-1. Memory Map ( µ PD78052, 78052Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 16384 × 8 b...
Page 92 - CHAPTER 5 CPU ARCHITECTURE
92 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD78053, 78053Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 24576 × 8 bits 5FFFH 1000H0FFFH 0800H07FFH 0080H 007FH 0040H003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal ...
Page 99 - The internal program memory space
99 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC). Each product of the µ PD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below. Tab...
Page 100 - The; Part Number; The internal high-speed RAM can also be used as a stack memory.; Caution Do not access addresses where the SFR is not assigned.
100 CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD78054 and 78054Y subseries units incorporate the following RAMs. (1) Internal high-speed RAM The µ PD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below. Table 5-3. Internal High-Speed RAM Cap...
Page 101 - and general registers. This area is between FD00H and FFFFH for the
101 CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is a...
Page 107 - memory size switching register.
107 CHAPTER 5 CPU ARCHITECTURE Figure 5-15. Data Memory Addressing ( µ PD78058, 78058Y) Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56K bytes by the memory size switching...
Page 109 - IE; Processor Registers; Figure 5-17. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 5-18. Program Status Word Configuration; acknowledged, and set to 1 when the EI instruction is executed.
109 CHAPTER 5 CPU ARCHITECTURE 7 0 IE PSW Z RBS1 AC RBS0 0 ISP CY 5.2 Processor Registers The µ PD78054 and 78054Y subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registe...
Page 110 - instruction execution.
110 CHAPTER 5 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupt...
Page 111 - Figure 5-19. Stack Pointer Configuration
111 CHAPTER 5 CPU ARCHITECTURE Figure 5-19. Stack Pointer Configuration The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-20 and 5-21. Caution Since RESET input mak...
Page 112 - processing and a register for interruption for each bank.
112 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two...
Page 113 - Figure 5-22. General Register Configuration; FEFFH
113 CHAPTER 5 CPU ARCHITECTURE BANK0 BANK1 BANK2 BANK3 FEFFH FEF8HFEF7H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16-Bit Processing 8-Bit Processing FEF0HFEEFH FEE8HFEE7H Figure 5-22. General Register Configuration (a) Absolute Name (b) Function Name BANK0 BANK1 BANK2 BANK3 FEFFH FEF8HFEF7H FEE0H R...
Page 116 - This register is provided only in the
116 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF38H FF39H FF3AH FF3BH FF40H Timer clock select register 0 TCL0 √ √ — FF41H Timer clock select register 1 TCL1 — √ — FF42H Timer clock select register 2 TCL2 — √ — FF43H Timer clock select register 3 ...
Page 118 - Instruction Address Addressing; of the next instruction.
118 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 8 7 6 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start addressof the instructionafter the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program co...
Page 119 - instruction branches to an area of addresses 0800H through 0FFFH.; In the case of CALLF !addr11 instruction
119 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !add...
Page 121 - Operand Address Addressing; manipulation during instruction execution.
121 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and...
Page 122 - Identifier
122 CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressin...
Page 123 - Operation code; Memory
123 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !ad...
Page 127 - can be carried out for all the memory spaces.
127 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the registe...
Page 129 - CHAPTER 6 PORT FUNCTIONS
129 Port 6 Port 0 Port 7 8 Port 1 Port 2 P00 P60 P67 P70 P72 P10 P07 P17 P20 P27 Port 13 Port 3 Port 4 P120 P127 P130 Port 12 P131 P30 P37 P40-P47 Port 5 P50 P57 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78054 and 78054Y subseries units incorporate two input ports and sixty-seven input/out...
Page 130 - CHAPTER 6 PORT FUNCTIONS
130 CHAPTER 6 PORT FUNCTIONS P10 to P17 ANI0 to ANI7 Pin Name Function Alternate Function P00 Input only INTP0/TI00 P01 INTP1/TI01 P02 Input/output mode can be specified in 1-bit INTP2 P03 Port 0. units. INTP3 P04 8-bit input/output port. When used as an input port, an on-chip INTP4 P05 pull-up resi...
Page 134 - Port Configuration; A port consists of the following hardware:; connection for subsystem clock oscillation.; the output mode is used, set the interrupt mask flag to 1.
134 CHAPTER 6 PORT FUNCTIONS Control register 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13) Pull-up resistor option register (PUOH, PUOL) Memory expansion mode register (MM) Not...
Page 135 - Internal bus; PM
135 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD P01/INTP1/TI01.P02/INTP2 P06/INTP6 Selector PUO0 Output Latch(P01 to P06) PM01-PM06 Internal bus P00/INTP0/TI00,P07/XT1 RD Internal bus Figure 6-2. P00 and P07 Block Diagram Figure 6-3. P01 to P06 Block Diagram PUO : Pull-up resistor opt...
Page 137 - Format and Figure 18-3 Serial Operating Mode Register 1 Format.
137 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch(P20, P21, P23-P26) PM20, PM21PM23-PM26 Internal bus Alternate Function P20/SI1,P21/SO1,P23/STB,P24/BUSY,P25/SI0/SB0,P26/SO0/SB1 6.2.3 Port 2 ( µ PD78054 Subseries) Port 2 is an 8-bit input/output port with outp...
Page 139 - 8-3 Serial Operating Mode Register 1 Format.
139 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23 to P26) PM20, PM21PM23 to PM26 Internal bus Alternate Function P20/SI1,P21/SO1,P23/STB,P24/BUSY,P25/SI0/SB0/SDA0,P26/SO0/SB1/SDA1 6.2.4 Port 2 ( µ PD78054Y Subseries) Port 2 is an 8-bit input/out...
Page 142 - KRMK; Figure 6-11. Block Diagram of Falling Edge Detection Circuit
142 CHAPTER 6 PORT FUNCTIONS P40 P41 P42 P43 P44 P45 P46 P47 Falling EdgeDetection Circuit KRMK KRIF Set Signal Standby ReleaseSignal P-ch WR MM WR PORT RD WR PUO V DD Selector PUO4 Output Latch(P40 to P47) MM Internal bus P40/AD0 P47/AD7 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output...
Page 144 - Pins P60 to P63 can drive LEDs directly.; depending on the following conditions:
144 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending ...
Page 150 - Port Function Control Registers; The following four types of registers control the ports.
150 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) ...
Page 153 - RESET input sets this register to 00H.; Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
153 CHAPTER 6 PORT FUNCTIONS PUO7 PUO6 PUO5 PUO4 PUO2 PUO1 PUO0 PUOL PUOm Pm Internal Pull-up Resistor Selection(m=0 to 7, 12, 13) 0 1 Internal pull-up resistor not used Internal pull-up resistor used FFF7H 00H R/W <7> <6> <5> <4> PUO3 <3> <2> <0> <1> ...
Page 154 - This register is used to set input/output of port 4.; Figure 6-21. Memory Expansion Mode Register Format
154 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21. Memory Expansion Mode Register Format Note The full address m...
Page 155 - KRM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-22. Key Return Mode Register Format
155 CHAPTER 6 PORT FUNCTIONS KRIF Key Return Signal Detection Flag 0 1 Not Detected Detected (Falling edge detection of port 4) 0 0 0 0 KRM FFF6H 7 6 5 4 3 2 Symbol <1> 0 KRMK KRIF <0> 0 KRMK Standby Mode Control by Key Return Signal 0 1 Standby mode release enabled Standby mode release ...
Page 156 - Port Function Operations
156 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents ar...
Page 157 - latch contents are output from the pins.; than the manipulated bit.; Selection of Mask Option; Table 6-6. Comparison between Mask ROM Version and PROM Version; Pin Name
157 CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until...
Page 159 - types of system clock oscillators are available.; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 7-1. Clock Generator Configuration
159 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5....
Page 160 - CHAPTER 7 CLOCK GENERATOR; Figure 7-1. Block Diagram of Clock Generator
160 CHAPTER 7 CLOCK GENERATOR Subsystem Clock Oscillator Main SystemClock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to PeripheralHardware Prescaler Oscillation ModeSel...
Page 161 - FRC; Clock Generator Control Register; The clock generator is controlled by the following two registers:; Figure 7-2. Subsystem Clock Feedback Resistor
161 CHAPTER 7 CLOCK GENERATOR FRC P-ch Feedback resistor XT1 XT2 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The...
Page 162 - Figure 7-3. Processor Clock Control Register Format; system clock oscillation. A STOP instruction should not be used.; Caution Bit 3 must be set to 0.; or f; : Subsystem clock oscillator frequency
162 CHAPTER 7 CLOCK GENERATOR MCC FRC CLS CSS PCC2 PCC1 PCC0 PCC CLS 0 1 Main system clock Subsystem clock FFFBH 04H R/W Note 1 <7> <5> <4> Symbol Address After Reset R/W 0 <6> 3 2 0 1 CSS 0 0 f XX /2 PCC2 CPU CIock (f CPU ) Selection PCC1 PCC0 CPU Clock Status 0 0 0 1 0 0 1 ...
Page 163 - The fastest instruction of the; ) and the minimum instruction execution time are as shown in; : Main system clock oscillation frequency; : Subsystem clock oscillation frequency
163 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78054 and 78054Y Subseries is executed with two clocks of the CPU clock. Therefore, relationships between the CPU clock (f CPU ) and the minimum instruction execution time are as shown in Table 7-2. Table 7-2. Relationship between CPU ...
Page 164 - OSMS is set with 8-bit memory manipulation instruction.; Figure 7-4. Oscillation Mode Selection Register Format; Remarks f
164 CHAPTER 7 CLOCK GENERATOR Write to OSMS (MCS 0) f XX Max. 2/f X Operating at f XX = f X /2 (MCS = 0) Operating at f XX = f X /2 (MCS = 0) MCS Main System Clock Scaler Control 0 1 Scaler used Scaler not used 0 0 0 0 OSMS FFF2H 7 6 5 4 3 2 Symbol 1 0 MCS 0 0 Address After Reset R/W 00H W 0 (2) Osc...
Page 165 - System Clock Oscillator; connected to the X1 and X2 pins.; Figure 7-6. External Circuit of Main System Clock Oscillator
165 CHAPTER 7 CLOCK GENERATOR Crystal orCeramic Resonator IC X1 X2 X1 PD74HCU04 µ X2 External Clock 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X...
Page 166 - and an antiphase clock signal to the XT2 pin.; PORTn
166 CHAPTER 7 CLOCK GENERATOR IC X2 X1 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to...
Page 167 - (d) Current flows through the grounding line; in series on the XT2 side.; between XT2 and X1 directly to V
167 CHAPTER 7 CLOCK GENERATOR IC X1 X2 IC X2 X1 High Current Figure 7-8. Examples of Incorrect Oscillator Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the oscillator (potential at points A, B, and C fluctuate) (e) Signals a...
Page 168 - The scaler divides the main system clock oscillator output (f; connect the XT1 and XT2 pins as follows.; pins as described above.
168 CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT...
Page 169 - Clock Generator Operations
169 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • Subsystem clock f XT • CPU clock f CPU • Clock to peripheral hardware The follow...
Page 170 - (b) Operation when MCC is set in case of main system clock operation
170 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock L L Oscillation does not stop. MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.1 Main system clock operations When operated with the main system clock (wi...
Page 171 - the following operations are carried out.; Changing System Clock and CPU Clock Settings
171 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.5.2 Subsystem clock operations When operated with the sub...
Page 172 - Table 7-3. Maximum Time Required for CPU Clock Switchover; MCS: Oscillation mode selection register bit 0
172 CHAPTER 7 CLOCK GENERATOR Table 7-3. Maximum Time Required for CPU Clock Switchover × × × × 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 CSS 0 0 0 0 × PCC0 PCC1 PCC2 1 × 1 PCC0 CSS PCC2 PCC1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 × 1 × × 1 8 instructions 2 instructions 4 instructions 4 instructions 16 instructions 2 ...
Page 173 - System clock and CPU clock switching procedure
173 CHAPTER 7 CLOCK GENERATOR V DD RESET Interrupt Request Signal System Clock CPU Clock Wait (26.2 ms : 5.0 MHz) Internal Reset Operation MinimumSpeedOperation Maximum SpeedOperation Subsystem ClockOperation f XX f XX f XT f XX High-SpeedOperation 7.6.2 System clock and CPU clock switching procedur...
Page 175 - Outline of Timers Incorporated in the; Subseries and related circuits are outlined below.
175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated in the µ PD78054, 78054Y Subseries This chapter explains 16-bit timer/event counter. Before that, the timers incorporated into the µ PD78054, 78054Y Subseries and related circuits are outlined below. (1) 16-bit timer/event c...
Page 177 - Values in parentheses when operated at f
177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width...
Page 179 - The 16-bit timer/event counter consists of the following hardware.; Refer to Figure 21-1. Basic Configuration of Interrupt Function.; Notes 1. Edge detection circuit
179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Configuration Timer register 16 bits × 1 (TM0) Register Capture/compare register: 16 bits ...
Page 181 - one pulse cannot be counted.; CR01 is set with a 16-bit memory manipulation instruction.
181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control re...
Page 184 - : Subsystem clock oscillation frequency; Figures in parentheses apply to operation with f; TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of osci...
Page 185 - When using the PWM mode, set the PWM mode and then set data to CR00.
185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 TMC03 TMC02 TMC01 OVF0 7 6 5 4 3 2 1 <0> Symbol TMC0 FF48H 00H R/W Address After Reset R/W OVF0 16-Bit Timer Register Overflow Detection 0 Overflow not detected 1 Overflow detected TMC03 TMC02 TMC01 Operating Mode Clear Mode Selection TO0 Output...
Page 186 - Cautions 1. Timer operation must be stopped before setting CRC0.; TOC0 is set with a 1-bit or 8-bit memory manipulation instruction.
186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5. Capture/Compar...
Page 187 - If LVS0 and LVR0 are read after data is set, they will be 0.
187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 7 <6> <5> 4 <3> <2> 1 <0> Symbol TOC0 FF4EH 00H R/W Address After Reset R/W TOE0 16-Bit Timer/Event Counter Output Control 0 Output disabled (Port mode) 1 Output enabled TOC01 0 1 In PWM Mod...
Page 188 - PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 7 6 5 4 3 2 1 0 Symbol PM3 FF23H FFH R/W Address After Reset R/W PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (5) Port mode register 3 (PM3) Thi...
Page 189 - Figure 8-8. External Interrupt Mode Register 0 Format
189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ES31 ES30 ES21 ES20 ES11 ES10 0 0 7 6 5 4 3 2 1 0 Symbol INTM0 FFECH 00H R/W Address After Reset R/W ES11 INTP0 Valid Edge Selection ES10 0 Falling edge 0 0 Rising edge 1 1 Setting prohibited 0 1 Both falling and rising edges 1 ES21 INTP1 Valid Edge Selection...
Page 190 - SCS is set with an 8-bit memory manipulation instruction.
190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0 SCS1 SCS0 7 6 5 4 3 2 1 0 Symbol SCS FF47H 00H R/W Address After Reset R/W SCS1 SCS0 0 0 0 1 1 0 1 1 INTP0 Sampling Clock Selection MCS = 1 MCS = 0 f XX /2 N f X /2 7 (39.1 kHz) f XX /2 7 f X /2 8 (19.5 kHz) f X /2 5 (156.3 kHz) f XX /2 5 f X /2 6...
Page 191 - the description of the respective control registers for details.; Clear & start on match TM0 and CR00
191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0/1 0/1 0 CRC02 CRC01 CRC00 CRC0 CR00 set as compare register 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in F...
Page 192 - Clear Circuit; Figure 8-11. Interval Timer Configuration Diagram
192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 16-Bit Capture/Compare Register 00 (CR00) 16-Bit Timer Register (TM0) Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 TI00/P00/INTP0 OVF0 Clear Circuit INTTM00 Figure 8-11. Interval Timer Configuration Diagram Figure 8-12. Interval Timer Operation Timings t Coun...
Page 193 - : Main system clock oscillation frequency; Figures in parentheses apply to operation with f; and the sub-cycle determined by 2; Be sure to write 0 to bits 0 and 1 of CR00.
193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 2 × TI00 input cycle 2 16 × TI00 input cycle TI00 input edge cycle 0 0 1 Setting 2 × 1/f X Settin...
Page 194 - PWM mode; Figure 8-13. Control Register Settings for PWM Output Operation
194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOE0 TOC01 LVR0 LVS0 TOC04 OSPE OSPT TOC0 1 0/1 × × × × × 0 TO0 Output Enabled Specifies Active Level CRC00 CRC01 CRC02 CRC0 0 0/1 0/1 0 0 0 0 0 CR00 set as compare register TMC0 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8-13. Control Register Se...
Page 195 - Switching Circuit; The analog output voltage (V; : External switching circuit reference voltage; Figure 8-14. Example of D/A Converter Configuration with PWM Output; synthesizer type TV tuner.; Figure 8-15. TV Tuner Application Circuit Example
195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PD78054, 78054Y µ TO0/P30 V SS 8.2 k Ω 8.2 k Ω 100 pF 22 k Ω +110 V 2SC 2352 47 k Ω 47 k Ω 47 k Ω 0.22 F µ 0.22 F µ 0.22 F µ Electronic Tuner GND PC574J µ Switching Circuit TO0/P30 PWM signal V REF Low-Pass Filter Analog Output (V AN ) PD78054, 78054Y µ By in...
Page 196 - Figure 8-16. Control Register Settings for PPG Output Operation
196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 1 0 0 0 TOE0 TOC01 LVR0 LVS0 Inversion of output on match of TM0 and CR00 TOC04 OSPE OSPT TO0 Output Enabled Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01One-shot pulse output disabled CRC0 0 x 0 0 0 0 0 ...
Page 197 - Pulse width measurement operations; eliminating noise with a short pulse width.; Free-Running Counter and One Capture Register
197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode CRC0 0 0/1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as capture register 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signal...
Page 198 - Count Clock; and One Capture Register (with Both Edges Specified)
198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) OVF0 INTP0 Internal Bus TI00/P00/INTP00 Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D1 FFFF 0000 D2 D...
Page 199 - (2) Measurement of two pulse widths with free-running counter; thus eliminating noise with a short pulse width.
199 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge ofTI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode (2) Measurement of two pulse widths with free-runn...
Page 200 - Figure 8-21. Timing of Pulse Width Measurement Operation with
200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) × t (10000H – D1 + D2) × t (10000H – D1 + (D2 + 1)) × t (D3 – D2) × t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8-21. Ti...
Page 201 - Free-Running Counter and Two Capture Registers
201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge ofTI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode (3) Pulse width measurement with free-running coun...
Page 202 - Counter and Two Capture Registers (with Rising Edge Specified)
202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1-D0) × t (10000H-D1 + D2) × t (D3-D2) × t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running C...
Page 203 - (4) Pulse width measurement by means of restart; with a short pulse width.; compare register 00 (CR00) cannot perform the capture operation.
203 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 0 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear & start with valid edge of TI00/P00 pin (4) Pulse width m...
Page 205 - Figure 8-27. External Event Counter Configuration Diagram
205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TI00 Pin Input TM0 Count Value CR00 INTTM0 N 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 INTP0 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) Internal Bus TI00 Valid Ed...
Page 206 - frequency to be output.; Figure 8-29. Control Register Settings in Square-Wave Output Mode
206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 0 0 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output EnabledInversion of output on match of TM0 and CR00Specified TO0 output F/F initial valueNo inversion of output on match of TM0 and CR01 One-shot pulse output disabled CRC0 0 0/1 0/1 0 0...
Page 210 - Clear & start with valid edge of TI00/P00 pin; P30 pin with a TI00/P00 valid edge as an external trigger.
210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as compare register TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 LVS0 OSPT OSPE TOC04 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial v...
Page 213 - (4) Capture register data retention timings; detection of the valid edge.; Figure 8-37. Capture Register Data Retention Timing
213 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse TM0 Count Value Edge Input Interrupt Request Flag Capture Read Signal CR01 Captured Value Capture OperationIgnored X N+1 N N+1 N+2 M M+1 M+2 (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit c...
Page 214 - OFV0 flag is set to 1 in the following case.; Figure 8-38. Operation Timing of OVF0 Flag
214 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from...
Page 215 - CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; • Interval timer
215 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is...
Page 216 - CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; Interrupt requests are generated at the preset time intervals.
216 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0...
Page 218 - Interrupt requests can be generated at the preset time intervals.
218 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interva...
Page 219 - Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2...
Page 222 - The section in the broken line is an output control circuit.; : Serial clock frequency; INV
222 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Remarks 1. The section ...
Page 224 - Figure 9-4. Timer Clock Select Register 1 Format; Figures in parentheses apply to operation with f
224 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4. Timer Clock Select Register 1 Format Caution When rewriting TCL1 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. TI1 : 8-...
Page 225 - TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
225 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET i...
Page 226 - timer registers 1 and 2.; Cautions 1. Be sure to set TOC1 after stopping timer operation.
226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bi...
Page 228 - Figure 9-8. Interval Timer Operation Timings
228 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the cou...
Page 229 - Values in parentheses when operated at f
229 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 0 TI1 input cycle 2 8 × TI1 input cycle TI1 input edge cycle 0 0 0 1 TI1 input cycle 2 8 ...
Page 231 - is input. Either the rising or falling edge can be selected.; TI1 Pin Input
231 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid e...
Page 232 - a square wave with any selected frequency to be output.
232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare register 10 and 20 (CR10, CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of t...
Page 234 - the overflow signal of TM1 becomes the count clock of TM2.; Figure 9-11. Interval Timer Operation Timing
234 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is set with bits 0 to 3 (TCL10 to TCL13) of timer clock sel...
Page 236 - falling edge can be selected.
236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2- channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specifi...
Page 238 - with the count pulse.; Count Pulse
238 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-13. Square-Wave Output Operation Timing Note The initial value of TO2 pin output can be set with the bits 6 and 7 (LVR2, LVS2) of 8-bit timer output control register (TOC1). 9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 (1) Timer start e...
Page 239 - Figure 9-15. Event Counter Operation Timing; is necessary to restart the timer after changing CR10 and CR20.; Interrupt Request Flag
239 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit compare register 10 and 20 setting The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out. When the 8-bit com...
Page 242 - CHAPTER 10 WATCH TIMER; Watch Timer Configuration
242 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration Counter 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers T...
Page 243 - Prescaler; Clear
243 CHAPTER 10 WATCH TIMER TMC21 Prescaler Selector INTWT 5-Bit Counter f W 2 14 f W 2 13 INTTM3 To 16-Bit Timer/Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Internal Bus TCL24 Timer ClockSelect Register 2 3 f W 2 4 f W 2 5 f W 2 6 f W 2 7 f W 2 8 f W 2 9...
Page 244 - Figure 10-2. Timer Clock Select Register 2 Format
244 CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscill...
Page 245 - RESET input sets TMC2 to 00H.; Figure 10-3. Watch Timer Mode Control Register Format
245 CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. ...
Page 246 - Watch Timer Operations; Table 10-3. Interval Timer Interval Time
246 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the co...
Page 248 - CHAPTER 11 WATCHDOG TIMER; MCS : Oscillation mode selection register bit 0
248 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.64 ms) 2 13 × ...
Page 249 - Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 11-3. Watchdog Timer Configuration; Item; Figure 11-1. Watchdog Timer Block Diagram; Control register
249 CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Timer clock select register 2 (TCL2) Watchdog timer mode control register (WDTM) Figure 11-1. Watchdog Timer Block Diagra...
Page 250 - Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
250 CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer...
Page 251 - Figure 11-2. Timer Clock Select Register 2 Format
251 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock osc...
Page 252 - WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 11-3. Watchdog Timer Mode Register Format
252 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format ...
Page 253 - Watchdog Timer Operations; Table 11-4. Watchdog Timer Runaway Detection Times
253 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be select...
Page 254 - requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time; Figures in parentheses apply to operation with f
254 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval tim...
Page 255 - CLOE; CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Follow the procedure below to output clock pulses.
255 CLOE PCL/P35 Pin Output * * CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer cloc...
Page 256 - CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Clock Output Control Circuit Configuration; Table 12-1. Clock Output Control Circuit Configuration; Figure 12-2. Clock Output Control Circuit Block Diagram
256 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Internal Bus f XX f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XT CLOE TCL03 TCL02 TCL01 TCL00 P35 Output Latch Synchronizing Circuit 4 PM35 Selector Timer Clock Select Register 0 Port Mode Register 3 PCL / P35 12.2 Clock Output Co...
Page 257 - Clock Output Function Control Registers; This register sets PCL output clock.
257 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets...
Page 258 - Figure 12-3. Timer Clock Select Register 0 Format
258 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CLOE <7> TCL06 6 TCL05 TCL04 4 TCL03 3 2 1 0 FF40H Address TCL0 Symbol TCL02 TCL01 TCL00 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 1 Other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 TCL03 TCL02 TCL01 f XT (32.768 kHz) f XX f XX / 2 f XX / 2 2...
Page 259 - Figure 12-4. Port Mode Register 3 Format
259 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Oscillatio...
Page 261 - CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 13-1. Buzzer Output Control Circuit Configuration; Figure 13-1. Buzzer Output Control Circuit Block Diagram
261 Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2....
Page 262 - CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Buzzer Output Function Control Registers; This register sets the buzzer output frequency.; watchdog timer count clock.
262 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register s...
Page 263 - Figure 13-2. Timer Clock Select Register 2 Format
263 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subs...
Page 264 - Figure 13-3. Port Mode Register 3 Format
264 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R / W R / W PM3n 0 1 P3n Pin Input /Output Mode Selection (n=0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Port mode register 3 (P...
Page 265 - CHAPTER 14 A/D CONVERTER
265 CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D ...
Page 266 - CHAPTER 14 A/D CONVERTER; Tap Selector; Bits 0 and 1 of external interrupt mode register 1 (INTM1)
266 CHAPTER 14 A/D CONVERTER ANI0/P10ANI1/P11ANI2/P12ANI3/P13ANI4/P14ANI5/P15ANI6/P16ANI7/P17 Selector A /D Converter Mode Register 3 Trigger Enable ES40, ES41 Note 3 Sample & Hold Circuit 3 CS ADIS3 4 Internal Bus Internal Bus EdgeDetector Control Circuit Series Resistor String AV DD VoltageCom...
Page 267 - ADCR is read with an 8-bit memory manipulation instruction.; and generates a voltage to be compared; or lower than AV; converted values of other channels.
267 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant...
Page 269 - • External interrupt mode register 1 (INTM1)
269 CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode registe...
Page 270 - Setting prohibited because A/D conversion time is less than 19.1
270 CHAPTER 14 A/D CONVERTER Figure 14-3. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of...
Page 271 - ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
271 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit me...
Page 272 - This register sets the valid edge for INTP3 to INTP6.; Figure 14-5. External Interrupt Mode Register 1 Format
272 CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5. External Interrupt Mode Register 1 Format ES71 7 ES70 6 ES61 ES60 ...
Page 273 - , the MSB of SAR remains set. If the input
273 CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D conv...
Page 274 - After RESET input, the value of ADCR is undefined.
274 CHAPTER 14 A/D CONVERTER Figure 14-6. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS...
Page 275 - Input voltage and conversion results
275 CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = ...
Page 276 - The following two ways are available to start A/D conversion.
276 CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode Select one analog input channel from ANI0 to ANI7 with A/D converter input select register (ADIS) and A/D converter mode register (ADM), and start A/D conversion. The following two ways are available to start A/D conversion. • Hardware...
Page 277 - continues repeatedly until new data is written to ADM.
277 CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of AD...
Page 278 - pin at this time, this current must
278 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV REF0 pin at this time, this cur...
Page 279 - Figure 14-11. Analog Input Pin Disposition
279 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF0 and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected...
Page 280 - pin; The AV; Therefore, be sure to apply the same voltage as V; to this pin even when the application circuit is designed; Pin
280 CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. If an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may ha...
Page 281 - CHAPTER 15 D/A CONVERTER; The conversion method used is the R-2R resistor ladder method.
281 CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by set...
Page 282 - CHAPTER 15 D/A CONVERTER; The D/A converter consists of the following hardware.
282 CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode r...
Page 283 - RESET input sets these registers to 00H.; trigger and before the next output trigger.; DACSn
283 CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values to determine analog voltage output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets t...
Page 284 - The DAM is set with a 1-bit or 8-bit memory manipulation instruction.; a pull-up resistor should be disconnected.
284 CHAPTER 15 D/A CONVERTER 0 7 0 6 DAM5 DAM4 4 0 3 2 <1> <0> FF98H Address DAM Symbol 0 DACE1 DACE0 5 00H After Reset R / W R / W DAM5 0 1 D/A Converter Channel 1 Operating Mode Normal mode Real-time output mode DACE0 0 1 D/A Converter Channel 0 Control D/A conversion stop D/A conversi...
Page 285 - with the output triggers.
285 CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D/A converter mode register (DAM), respectively. (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to ...
Page 286 - Figure 15-3. Use Example of Buffer Amplifier; When only either one of the D/A converter channels is used with AV; , the other pins that are not used; low level from the pin.
286 CHAPTER 15 D/A CONVERTER PD78054, 78054Y ANOn R R 1 C • The input impedance of the buffer amplifier is R 1 . • If R 1 is not connected, the output becomes undefined when RESET is low. µ 15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of t...
Page 287 - CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) The µ PD78054 subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to C...
Page 288 - CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions
288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not switch the ...
Page 289 - more devices can be used as input/output ports.; Master CPU
289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by c...
Page 290 - Serial Interface Channel 0 Configuration; Table 16-2. Serial Interface Channel 0 Configuration
290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address regis...
Page 291 - Figure 16-2. Serial Interface Channel 0 Block Diagram
291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-2. Serial Interface Channel 0 Block Diagram Remark Output Control performs selection between CMOS output and N-ch open-drain output. CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Contr...
Page 292 - SIO0 is set with an 8-bit memory manipulation instruction.
292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-b...
Page 293 - is used, the circuit also controls clock output to the SCK0/P27 pin.
293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled also by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter c...
Page 294 - Serial Interface Channel 0 Control Registers
294 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus inte...
Page 295 - Figure 16-3. Timer Clock Select Register 3 Format
295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscill...
Page 296 - function and displays the address comparator match signal.
296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit...
Page 297 - ) the operation of serial interface channel
297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-4. Serial Operating Mode Register 0 Format (2/2) Notes 1. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register (SINT) to 0. 2. When CSIE0 = 0, COI becomes 0. 3. In the SBI mode...
Page 298 - SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5. Ser...
Page 300 - SINT is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 16-6. Interrupt Timing Specify Register Format; SVA
300 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET i...
Page 301 - Serial Interface Channel 0 Operations; • Operation stop mode
301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 16.4.1 Operation stop mod...
Page 302 - CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
302 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75...
Page 305 - SI0 pin is latched in SIO0 at the rising edge of SCK0.; RELT
305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial...
Page 306 - Figure 16-9. Circuit of Switching in Transfer Bit Order; conditions are satisfied.
306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figu...
Page 307 - the board can be decreased.; Figure 16-10. Example of Serial Bus Configuration with SBI
307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus co...
Page 308 - software, the software must be heavily loaded.; (b) Chip select function by address transmission; The busy signal to report the slave busy state is controlled.
308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge t...
Page 309 - The dotted line indicates READY status.; Address Transfer
309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, ...
Page 310 - This signal is output by the master device.
310 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output...
Page 311 - in order to select a particular slave device.; Figure 16-15. Slave Selection with Address
311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses 8-bit data following bus release and command signa...
Page 312 - by address transmission.; Data
312 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands Figure 16-17. Data 8-bit data following a command signal is def...
Page 313 - [When output in synchronization with 11th clock SCK0]
313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] [When output in synchro...
Page 314 - terminates the output of SCK0 serial clock.
314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device ...
Page 320 - ACKT
320 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-22. ACKT Operation Caution Do not set ACKT before termination of transfer. SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output fora period of one clockjust after setting
Page 321 - (b) When set after completion of transfer; ACKE
321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer (b) When set after completion of transfer (c) When ACKE = 0 upon completion of transfer (d) When “ACKE = 1” period is short SB0 (SB1) ACKE 1 2 7 8 9 D7 D6 D2 D...
Page 322 - (a) When ACK signal is output at 9th clock of SCK0
322 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 (b) When ACK signal is output after 9th clock of SCK0 (c) Clear timing when transfer start is instructed in BUSY Figure 16-25. BSYE Operation SCK0 SB0 (SB...
Page 324 - In BUSY state, transfer starts after the READY state is set.
324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal Synchronous clock to output address/command/ data, ACK signal, synchronous BUSY signal, etc. Address/command/ data are transferred wit...
Page 326 - of using the address match detection method.; two or more devices by outputting an “address” to the serial bus.
326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave addre...
Page 329 - Figure 16-29. Data Transmission from Master Device to Slave Device
329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-29. Data Transmission from Master Device to Slave Device 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operatio...
Page 330 - Figure 16-30. Data Transmission from Slave Device to Master Device
330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-30. Data Transmission from Slave Device to Master Device 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Reception INTCSI0 Generation ACK Output SerialReception Hardware Ope...
Page 331 - write FFH to SIO0 in advance.; before the first byte of serial transmission.
331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal...
Page 332 - transfer of the 1st byte after RESET input.
332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (10) Discrimination of slave busy state When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal gene...
Page 333 - Master
333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1...
Page 336 - CSIIF0 : Interrupt request flag corresponding to INTCSI0
336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Be sure to...
Page 337 - is carried out bit-wise in synchronization with the serial clock.
337 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial ...
Page 338 - Figure 16-33 shows RELT and CMDT operations.
338 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following t...
Page 339 - normal serial clock output.
339 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK...
Page 341 - CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) The µ PD78054Y subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to...
Page 342 - CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions; Serial interface channel 0 employs the following four modes.; transfer processing time.
342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I 2 C (Inter IC) bus mode Caution Do not switch the opera...
Page 343 - This mode is in compliance with the I; Figure 17-1. Serial Bus Configuration Example Using I
343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus forma...
Page 344 - Serial Interface Channel 0 Configuration; Table 17-2. Serial Interface Channel 0 Configuration
344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address regi...
Page 345 - Figure 17-2. Serial Interface Channel 0 Block Diagram
345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-2. Serial Interface Channel 0 Block Diagram Remark Output Control selects between CMOS output and N-ch open drain output. CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit...
Page 348 - Serial Interface Channel 0 Control Registers
348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus int...
Page 349 - Figure 17-3. Timer Clock Select Register 3 Format
349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscil...
Page 351 - Figure 17-4. Serial Operating Mode Register 0 Format; C bus mode, the clock frequency becomes 1/16 of that output from TO2.
351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for tr...
Page 353 - Notes 1. Setting should be performed before transfer.; However, the BSYE flag is not cleared to 0.; Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The busy...
Page 354 - RESET input sets SINT to 00H.; When not using the I
354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET ...
Page 355 - Notes 1. When using wake-up function in the I
355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 0. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA : Slave address register CSIIF0 : Interrupt request flag co...
Page 356 - Serial Interface Channel 0 Operations
356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I 2 C (Inter IC) bus mode 17.4.1 ...
Page 360 - Figure 17-9. Circuit of Switching in Transfer Bit Order
360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the fig...
Page 366 - Figure 17-12 shows RELT and CMDT operations.
366 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following ...
Page 367 - C bus mode operation; The I; Figure 17-13. Example of Serial Bus Configuration Using I
367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single ma...
Page 368 - C bus mode functions
368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals...
Page 369 - is the slave device which will send data to the master.; Figure 17-17. Transfer Direction Specification; Transfer direction
369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA...
Page 370 - the master device outputs no acknowledge signal in this case.
370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data tran...
Page 371 - to preparing for transmitting or receiving data.
371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continu...
Page 373 - SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 la...
Page 374 - Notes 1. This setting must be performed prior to transfer start.
374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) R/W ACKE Acknowledge Signal Automatic Output Control Note 1 0 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmittingdata. Note 2 1 Enabled.After completion of transfer, acknowledge signal ...
Page 375 - SINT is set by the 1-bit or 8-bit memory manipulation instruction.
375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. R/W WAT1 WAT0 Interrupt control by wait (See Note 2 ) 0 0 Interrupt service request is...
Page 376 - A list of signals in the I; C Bus Mode
376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 17-4. Table 17-4. Signals in I 2 C Bus Mode Signal name Description Start condition Definition : SDA0 (SDA1) falling edge when SCL is high Note 1 Function :...
Page 377 - In the I
377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1> Master ..... N-ch open-drain output...
Page 378 - (a) Comparison of SIO0 data before and after transmission
378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (7) Error detection In the I 2 C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) ...
Page 379 - Figure 17-22. Data Transmission from Master to Slave
379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address L L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L SIO0 ← Ad...
Page 382 - Figure 17-23. Data Transmission from Slave to Master
382 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 ← Addres...
Page 385 - C bus mode
385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start cond...
Page 386 - output latch to 1 after execution of an SIO0 write instruction.
386 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave s...
Page 390 - To internal logic
390 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB...
Page 391 - Figure 17-29. Logic Circuit of SCL Signal
391 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-29. Logic Circuit of SCL Signal Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2. CLC: Bit 3 of interrupt timing specify register (SINT) CLC (manipulated by bit manip...
Page 393 - Serial interface channel 1 employs the following three modes.
393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used...
Page 394 - CHAPTER 18 SERIAL INTERFACE CHANNEL 1; Serial Interface Channel 1 Configuration; Table 18-1. Serial Interface Channel 1 Configuration
394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive a...
Page 395 - Figure 18-1. Serial Interface Channel 1 Block Diagram
395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram RE ARLD ERCE ERR TRF STRB BUSY 1 BUSY 0 Internal Bus Automatic DataTransmit/ReceiveControl Register Serial OperatingMode Register 1 ADTI 7 ADTI 4 ADTI 3 ADTI 2 ADTI 1 ADTI 0 5-Bit Counter Serial I/O Shift...
Page 396 - SIO1 is set with an 8-bit memory manipulation instruction.; RESET input sets ADTP to 00H.
396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation ...
Page 397 - Serial Interface Channel 1 Control Registers; • Serial operating mode register 1 (CSIM1)
397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive contro...
Page 398 - Figure 18-2. Timer Clock Select Register 3 Format
398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. MCS...
Page 399 - CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 18-3. Serial Operation Mode Register 1 Format
399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instru...
Page 400 - execution and error detection.
400 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic transmit/receive enable/disable, the operating mode, strobe output enable/ disable, busy input enable/disable, error check enable/disable and displays automatic transmit...
Page 401 - Notes 1. The interval is dependent only on CPU processing.
401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure...
Page 402 - , the minimum interval time
402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). ...
Page 405 - Serial Interface Channel 1 Operations; Notes 1. Can be used freely as port function.
405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation ...
Page 407 - pin is latched into SIO1 at the rising edge of SCK1.
407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (...
Page 408 - Figure 18-7. Circuit of Switching in Transfer Bit Order
408 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read...
Page 411 - ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Notes 1. Bits 3 and 4 (TRF and ERR) are Read-Only bits. 2. The termination of automatic transmission/...
Page 412 - Main system clock frequency (f
412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Note...
Page 416 - subtracting 1 from the number of transmit data bytes.
416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order...
Page 417 - transmitted or received.; Figure 18-8. Basic Transmission/Reception Mode Operation Timings; CSIIF1 : Interrupt request flag; TRF
417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data i...
Page 418 - ADTP : Automatic data transmit/receive address pointer
418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive...
Page 419 - is transferred from the buffer RAM to SIO1.; FADFH
419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD=0, RE=1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (Refer to Figure 18-10 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger...
Page 421 - BUSY pins can be used as normal input/ports.; Figure 18-11. Basic Transmission Mode Operation Timings
421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM...
Page 422 - Figure 18-12. Basic Transmission Mode Flowchart; ADTP : Automatic data transmit/receive address pointer
422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive control ...
Page 423 - Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-13 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferr...
Page 425 - are transmitted again.; Figure 18-14. Repeat Transmission Mode Operation Timing; Interval
425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (C...
Page 426 - Figure 18-15. Repeat Transmission Mode Flowchart
426 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 Start Write transmit data in buffer RAM Set ADTP to th...
Page 428 - (b) Upon completion of transmission of 6 bytes
428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes (c) 7th byte transmission point Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Trans...
Page 429 - is suspended upon completion of 8-bit data transfer.
429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception...
Page 430 - device and slave device.; Master Device
430 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization Control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Bu...
Page 431 - The busy signal cannot be controlled with an external clock.; CSIIF1: Interrupt request flag
431 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Ca...
Page 432 - or receiving can wait while the busy signal is being input.
432 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device. When sending or receiving of 8 bit data...
Page 434 - (c) Bit Slippage Detection Function Through the Busy Signal; bit slippage can be detected.; CSIIF1 : Interrupt Request Flag
434 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the s...
Page 435 - interval may be longer than the value indicated by paragraph (b).; CSIIF1: Interrupt request flag
435 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit...
Page 439 - Serial interface channel 2 has the following three modes.
439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is n...
Page 440 - CHAPTER 19 SERIAL INTERFACE CHANNEL 2; Serial Interface Channel 2 Configuration; Table 19-1. Serial Interface Channel 2 Configuration
440 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive b...
Page 441 - Figure 19-1. Serial Interface Channel 2 Block Diagram; See Figure 19-2 for the baud rate generator configuration.
441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1. Serial Interface Channel 2 Block Diagram Note See Figure 19-2 for the baud rate generator configuration. Internal Bus Asynchronous Serial Interface Mode Register AsynchronousSerial InterfaceStatus Register Receive Buffer Register (RXB/SIO2) Dire...
Page 442 - Figure 19-2. Baud Rate Generator Block Diagram
442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2. Baud Rate Generator Block Diagram TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Transmit Clock 1/2 Selector Receive Clock Match Match MD...
Page 443 - Writing data to TXS starts the transmit operation.; RXS cannot be directly manipulated by a program.
443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writi...
Page 444 - Serial Interface Channel 2 Control Registers; Figure 19-3. Serial Operating Mode Register 2 Format
444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status...
Page 445 - ASIM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 19-4. Asynchronous Serial Interface Mode Register Format
445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. 2. The serial transmit/receive operation must be s...
Page 446 - Table 19-2. Serial Interface Channel 2 Operating Mode Settings; TXE RXE SCK CSIE2 CSIM22 CSCK
446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmi...
Page 447 - will continue to be generated until RXB is read.
447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read. 2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interfa...
Page 448 - BRGC is set with an 8-bit memory manipulation instruction.; Baud Rate Generator Input Clock Selection
448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6. Baud Rate Generator Control Register For...
Page 450 - scaled from the clock input from the ASCK pin.; Table 19-3. Relation between Main System Clock and Baud Rate; MCS: Oscillation mode selection register bit 0
450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...
Page 451 - Frequency of clock input to ASCK pin
451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with ...
Page 452 - Serial Interface Channel 2 Operation
452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial trans...
Page 454 - CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
454 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide r...
Page 456 - ASIS is set with a 1-bit or 8-bit memory manipulation instruction.
456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun erro...
Page 459 - a signal scaled from the clock input from the ASCK pin.; Table 19-5. Relation between Main System Clock and Baud Rate
459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...
Page 461 - One data frame consists of the following bits.; Stop Bit
461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame consists of the following bits. • Start bits .................. 1 ...
Page 462 - Even parity
462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) erro...
Page 463 - Interrupt Request Generation Timing
463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TX...
Page 464 - start bit, reception of one frame of data ends.; Figure 19-9. Asynchronous Serial Interface Reception Completion
464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When the bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by AS...
Page 466 - FFH, then set the TXE to 1 before executing the next transmission.; The State of Receive Buffer Register (RXB) and Whether
466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 bef...
Page 472 - received bit by bit in synchronization with the serial clock.; SRIF
472 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift regist...
Page 473 - Figure 19-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
473 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be rea...
Page 474 - Limitations when UART mode is used; ISRM : Bit 1 of asynchronous serial interface mode register (ASIM); : Source clock of 5-bit counter of baud rate generator; Countermeasures
474 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Limitations when UART mode is used In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception error interrupt request (INTSER) has occurred and then cleared. Consequently, the following phenomenon ma...
Page 475 - • In case of parity error; Example of preventive measures; Here is an example of the above preventive measures.
475 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 • In case of parity error Disable the receive buffer register (RXB) from being read for a certain time (T1 + T2 in Figure 19-15) after the reception error interrupt request (INTSER) has occurred. Figure 19-15. Receive Buffer Register Read Disable Period T1 :...
Page 477 - CHAPTER 20 REAL-TIME OUTPUT PORT
477 CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt requests or external interrupt request generation, then output externally. This i...
Page 478 - CHAPTER 20 REAL-TIME OUTPUT PORT; Real-Time Output Port Configuration; The real-time output port consists of the following hardware.
478 CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Port mode register 12...
Page 480 - Real-Time Output Port Control Registers; The following three registers control the real-time output port.; Figure 20-3. Port Mode Register 12 Format; RTPM is set with a 1-bit or 8-bit memory manipulation instruction.
480 CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM...
Page 481 - Table 20-3. Real-time Output Port Operating Mode and Output Trigger
481 CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or...
Page 483 - The following three types of interrupt functions are used.
483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is ...
Page 484 - CHAPTER 21 INTERRUPT AND TEST FUNCTIONS; Interrupt Sources and Configuration; is the highest priority and 20 is the lowest priority.
484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Interrupt sources includes total of 22 non-maskbale, maskable, software interrupts (refer to Table 21-1). Table 21-1. Interrupt Source List (1/2) Interrupt Source Name Trigger Watchdog timer overflow (with watchdog ...
Page 485 - is the highest priority and 18 is the lowest priority.
485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Interrupt Source Name Trigger Reference time interval signal from watch timer Generation of 16-bit timer register, capture/compare register (CR00) match signal Generation of 16-bit timer register, capture/compare reg...
Page 488 - Interrupt Function Control Registers; to interrupt request sources.
488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag regis...
Page 489 - or upon application of RESET input.; Figure 21-2. Interrupt Request Flag Register Format
489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PIF6 Symbol IF0L <6> PIF5 <5> PIF4 <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> TMIF4 Address FFE0H 00H After Reset R/W R/W × × IF × 0 1 Interrupt Request Flag No interrupt request signal Interrupt request sig...
Page 490 - RESET input sets these registers to FFH.; Figure 21-3. Interrupt Mask Flag Register Format
490 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PMK6 Symbol MK0L <6> PMK5 <5> PMK4 <4> PMK3 <3> PMK2 <2> PMK <1> PMK <0> TMMK4 Address FFE4H FFH After Reset R/W R/W × × MK × 0 1 Interrupt Servicing Control Interrupt servicing enabled Interrupt servicin...
Page 491 - Set always 1 in PR1L bits 3 through 7.; Figure 21-4. Priority Specify Flag Register Format
491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PPR6 Symbol PR0L <6> PPR5 <5> PPR4 <4> PPR3 <3> PPR2 <2> PPR1 <1> PPR0 <0> TMPR4 Address FFE8H FFH After Reset R/W R/W 0 1 Priority Level Selection High priority level Low priority level <7> TMPR01 ...
Page 492 - These registers set the valid edge for INTP0 to INTP6.; Figure 21-5. External Interrupt Mode Register 0 Format
492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 0 0 0 0 1 0 1 ES10 0 0 1 1 INTP1 Valid Edge Sel...
Page 493 - Figure 21-6. External Interrupt Mode Register 1 Format
493 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES71 Symbol INTM1 6 ES70 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Ed...
Page 495 - Sampling Clock; Sampling Clock
495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS t SMP Sampling Clock INTP0 PIF0 "L" Because INTP0 level is not high level at the time of sampling,PIF0 flag remains at low level. t SMP Sampling Clock INTP0 PIF0 <1> <2> Because the sampled INTP0 level is high level twice in succession ...
Page 496 - processing are mapped.; Figure 21-9. Program Status Word Configuration
496 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt p...
Page 497 - Interrupt Servicing Operations; table contents are loaded into PC and branched.
497 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priori...
Page 498 - WDTM; Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing; : Watchdog timer interrupt request flag
498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt request selected)? Interrupt request generation WDT interrupt servicing? Interrupt control register unaccessed? Interrupt service start Interrupt request hel...
Page 499 - If a new non-maskable interrupt request is generated during; Main Routine
499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskab...
Page 500 - Maskable interrupt request acknowledge operation
500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrup...
Page 501 - Start
501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm ×× IF : Interrupt request flag ×× MK : Interrupt mask flag ×× PR : Priority specify flag IE : Flag to control acknowledgment of maskable interrupt request (1 = enable, 0 = disable) ISP : Flag...
Page 503 - Software interrupt request acknowledge operation; servicing, and set interrupt enable state.
503 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents is saved in the stacks, ...
Page 504 - Example 1. A multiple interrupt is generated at twice
504 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing EI INTxx(PR=1) INTyy(PR=0) IE=0 EI RETI INTxxServicing INTzz(PR=0) IE=0 EI RETI INTyyServicing IE=0 RETI INTzzServicing Figure 21-16. Multiple Interrupt Example (1/2) Example 1. A multiple interrupt is generated at twice While servicing int...
Page 505 - after execution of one main processing instruction.
505 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing INTxxServicing INTyyServicing INTxx(PR=0) 1 InstructionExecution IE=0 INTyy(PR=0) IE=0 RETI RETI EI Figure 21-16. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupt is disabled Because interr...
Page 506 - CPU processing
506 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated during processing of the instruction until the execution of the next instruction is completed. The following show...
Page 507 - Figure 21-18. Basic Configuration of Test Function
507 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal bus MK IF Test input signal Standbyrelease signal 21.5 Test Functions Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4, the corresponding test input flag is set (1) and a standby release signal is gen...
Page 508 - It indicates whether a watch timer overflow is detected or not.
508 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure...
Page 509 - Figure 21-21. Key Return Mode Register Format; timer overflow cycle.
509 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 0 Symbol KRM 6 0 5 0 4 0 3 0 2 0 <1> KRMK <0> KRIF Address FFF6H 02H WhenReset R/W R/W 0 1 Key Return Signal Not detected Detected (port 4 falling edge detection) KRIF 0 1 Standby Mode Control by Key Return Signal Standby mode release enabled...
Page 511 - Table 22-1. Pin Functions in External Memory Expansion Mode
511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/wr...
Page 512 - CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION; Memory map of
512 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map when Using External Device Expansion Function (1/4) (a) Memory map of µ PD78P054, 78P058, (b) Memory map of µ PD78P054, 78P058, 78P058Y when the µ P...
Page 514 - when the
514 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (3/4) (e) Memory map of µ PD78P058, 78P058Y when the µ PD78056, 78056Y and internal PROM are 48 Kbytes FFFFH SFR Internal High-Speed RAM F F 0 0 HF E F F H F B 0 0 HF A F F H FAE0H...
Page 515 - less than 56 Kbytes by the memory size switching register (IMS).; Reserved
515 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (4/4) (f) µ PD78058, 78058Y, 78P058, 78P058Y Memory (g) µ PD78058, 78058Y, 78P058, 78P058Y Memory map when internal ROM (PROM) size is map when internal ROM (PROM) size is 56 Kbyte...
Page 516 - External Device Expansion Function Control Register; RESET input sets this register to 10H.; Figure 22-2. Memory Expansion Mode Register Format
516 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 7 0 Symbol MM 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H 10H WhenReset R/W R/W MM2 MM1 MM0 Single-chip/Memory ExpansionMode Selection P40-P47, P50-P57, P64-P67 Pin state P40-P47 P50-P53 P54, P55 P56, P57 P64-P67 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1...
Page 517 - Figure 22-3. Memory Size Switching Register Format
517 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 1 1 48 Kbytes 56 Kbytes 1 1 0 1 0 0 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H Note After Reset R/W R/W Internal ROM size selection ROM3 60 Kbytes 1 ROM2 1 ROM1 1 ROM0 1 Setting prohibited Other than above Internal ...
Page 518 - External Device Expansion Function Timing; from external memory.
518 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data access...
Page 519 - Figure 22-4. Instruction Fetch from External Memory
519 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD Lower Address Operation Code AD0-AD7 A8-A15 Higher Address WAIT ASTB RD A...
Page 520 - Figure 22-5. External Memory Read Timing
520 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD Lower Address Read Data AD0-AD7 A8-A15 Higher Address WAIT ASTB RD AD0-AD7 A8-A15 Lo...
Page 521 - Figure 22-6. External Memory Write Timing
521 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB WR Higher Address AD0-AD7 A8-A15 WAIT Hi-Z Lower Address Write Data ASTB WR AD0-AD7 A8...
Page 522 - Figure 22-7. External Memory Read Modify Write Timing
522 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD WR Higher Address AD0-AD7 A8-A15 WAIT Hi-Z Lower Address Write Data Rea...
Page 523 - Example of Connection with Memory; This section provides
523 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION µ PD43256B CS OE A0-A14 I/O1-I/O8 WE AddressBus V DD µ PD78054 µ PD74HC573 LE D0-D7 Q0-Q7 OE RD WR A8-A14 ASTB AD0-AD7 DataBus V DD 22.4 Example of Connection with Memory This section provides µ PD78054 and external memory connection examples in Figu...
Page 525 - intermittent operations such as in watch applications.; request, it enables intermittent operations to be carried out.; the main system clock or the subsystem clock.
525 CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended ...
Page 526 - CHAPTER 23 STANDBY FUNCTION; Standby function control register; OSTS is set with an 8-bit memory manipulation instruction.; Values in parentheses apply to operating at f
526 CHAPTER 23 STANDBY FUNCTION Address FFFAH 04H After Reset R/W R/W 0 0 0 0 1 Selection of Oscillation StabilizationTime when STOP Mode is Released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx OSTS2 7 0 Symbol OSTS 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 0 0 1 1 0 Other than above OSTS1 ...
Page 527 - Standby Function Operations; The operating status in the HALT mode is described below.; Notes 1. Including when external clock is not supplied
527 CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. ...
Page 528 - (a) Clear upon unmasked interrupt request; status is acknowledged.
528 CHAPTER 23 STANDBY FUNCTION HALTInstruction InterruptRequest Wait StandbyRelease Signal OperatingMode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request When an unmas...
Page 529 - Figure 23-3. HALT Mode Release by RESET Input; : main system clock oscillation frequency; Table 23-2. Operation after HALT Mode Release
529 CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input When a RESET signal is input, the HALT mode is released, and as is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Remarks 1. f X : main syst...
Page 530 - via a pull-up resistor; The operating status in the STOP mode is described below.
530 CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to m...
Page 531 - (a) Release by unmasked interrupt request
531 CHAPTER 23 STANDBY FUNCTION STOPInstruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status OperatingMode Oscillation OperationgMode STOP Mode Oscillation Stop Oscillation StandbyRelease Signal Clock InterruptRequest (2) STOP mode release The STOP mode can be cleared with the follo...
Page 532 - Figure 23-5. Release by STOP Mode RESET Input; Table 23-4. Operation after STOP Mode Release
532 CHAPTER 23 STANDBY FUNCTION RESETSignal OperatingMode Clock ResetPeriod STOP Mode Oscillation Stop Oscillation StabilizationWait Status OperatingMode Oscillation Wait (2 17 /f x : 26.2 ms) STOPInstruction Oscillation (c) Release by RESET input When a RESET signal is input, the STOP mode is relea...
Page 533 - CHAPTER 24 RESET FUNCTION; (2) Internal reset by watchdog timer overrun time detection; Cautions 1. For an external reset, input a low level for 10
533 RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over-flow ResetSignal InterruptFunction CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer ...
Page 534 - Figure 24-2. Timing of Reset Input by RESET Input
534 CHAPTER 24 RESET FUNCTION RESET InternalReset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period(Oscillation Stop) OscillationStabilizationTime Wait Normal Operation(Reset Processing) Stop Status(Oscillation Stop) STOP Instruction Execution X1 Normal Operation WatchdogTimerOverflo...
Page 535 - CHAPTER 24 RESET FUNCTION; The values after reset depend on the product.
535 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (1/2) Hardware Status after Reset Program counter (PC) Note1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H Data memory Undefined Note2 General register Un...
Page 537 - CHAPTER 25 ROM CORRECTION; ROM Correction Configuration; Table 25-1. ROM Correction Configuration
537 Match CORENn CORSTn Program counter (PC) Comparator Correction addressregister (CORADn) Internal bus Correction control register Correction branch requestsignal (BR !7FDH) CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The µ PD78058, 78058Y subseries can replace part of a program in the...
Page 538 - RESET input sets CORAD0 and CORAD1 to 0000H.; Figure 25-2. Correction Address Registers 0 and 1 Format
538 CHAPTER 25 ROM CORRECTION FF3AH/FF3BH 0000H Symbol 15 CORAD0 0 Address FF38H/FF39H State after reset 0000H R/W R/W CORAD1 R/W (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM...
Page 539 - ROM Correction Control Registers; RESET input sets CORCN to 00H.; Figure 25-3. Correction Control Register Format
539 CHAPTER 25 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH State after reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address register 0 and fetch address match detection Not detected Detected Correction address register 0 and ...
Page 540 - ROM Correction Application; EEPROM; EEPROM; FFH
540 CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM TM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program a...
Page 541 - expansion RAM with the main program.
541 CHAPTER 25 ROM CORRECTION No Yes Initialization Load the contents of external nonvolatile memoryinto internal expansion RAMCorrection address register settingROM correction enabled Is ROM correction used ? Note ROM correction Main program (2) Assemble in advance the initialization routine as sho...
Page 543 - Internal ROM; ROM Correction Example; address value after the main program is started.
543 CHAPTER 25 ROM CORRECTION ADD A, #2 BR !1002H BR !F702H ADD A, #1 MOV B, A 0000H 0080H Program start 1000H 1002H Internal ROM Internal expansion RAM F400H F702H F7FDH F7FFH (1) (2) (3) EFFFH 25.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #...
Page 544 - Program Execution Flow; Area filled with diagonal lines : Internal expansion RAM
544 CHAPTER 25 ROM CORRECTION Correction place Internal ROM Internal ROM JUMP FFFFH F7FFH F7FDH xxxxH 0000H (1) (2) (3) BR !JUMP Correction program 25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9. Program Transition...
Page 545 - (2) Branches to branch destination judgment program
545 CHAPTER 25 ROM CORRECTION Internal ROM Correction place 1 Internal ROM JUMP Internal ROM (1) (2) (3) (4) (5) (6) (7) (8) FFFFH F7FFH F7FDH yyyyH xxxxH 0000H BR !JUMP Destination judge program Correction program 2 Correction program 1 Correction place 2 Figure 25-10. Program Transition Diagram (w...
Page 546 - Cautions on ROM Correction
546 CHAPTER 25 ROM CORRECTION 25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag ...
Page 549 - Table 26-3. Examples of Memory Size Switching Register Settings (; Relevant Mask ROM Version
549 CHAPTER 26 µ PD78P054, 78P058 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H C8H After Reset R/W R/W 1 Internal ROM Capacity selection 32 Kbytes ROM3 0 ROM2 0 ROM1 0 ROM0 Setting prohibited Other than above Internal High-Speed RAM Capacity Selection RAM2 RAM1 RAM0 ...
Page 550 - Table 26-4. Examples of Memory Size Switching Register Settings (
550 CHAPTER 26 µ PD78P054, 78P058 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H CFH After Reset R/W R/W 1 Internal ROM Capacity selection 32 Kbytes ROM3 0 ROM2 0 ROM1 0 ROM0 Setting prohibited Other than above Internal High-Speed RAM Capacity Selection RAM2 RAM1 RAM0 ...
Page 551 - Internal Expansion RAM Size Switching Register
551 CHAPTER 26 µ PD78P054, 78P058 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal extension RAM capacity selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 1 0 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 1 1 0 0 26.3 Internal Expansion RA...
Page 552 - PROM Programming; Caution In case of the; Table 26-6. PROM Programming Operating Modes
552 CHAPTER 26 µ PD78P054, 78P058 26.4 PROM Programming The µ PD78P054 and 78P058 incorporate a 32-Kbyte and 60-Kbyte PROM as program memory, respectively. To write a program into the µ PD78P054 or 78P058 PROM, make the device enter the PROM programming mode by setting the levels of the V PP and RES...
Page 554 - N = Last address of program; Figure 26-4. Page Program Mode Flowchart
554 CHAPTER 26 µ PD78P054, 78P058 Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1-ms program pulse Verify 4 Bytes Pass Address = N? No Pass V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified?...
Page 556 - Figure 26-6. Byte Program Mode Flowchart
556 CHAPTER 26 µ PD78P054, 78P058 Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X = 10? Address = Address + 1 Remark...
Page 557 - Cautions 1. Be sure to apply V; before applying V; , and remove it after removing V; to the V; pin may have an adverse affect on device reliability.
557 CHAPTER 26 µ PD78P054, 78P058 Figure 26-7. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing V PP . 2. V PP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +1...
Page 558 - pin. Unused pins are handled as shown in paragraph,; and V; (3) Input the address of data to be read to pins A0 through A16.
558 CHAPTER 26 µ PD78P054, 78P058 Address Input A0-A16 CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 26.4.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused pin...
Page 559 - Screening of One-Time PROM Versions
559 CHAPTER 26 µ PD78P054, 78P058 26.5 Erasure Procedure ( µ PD78P054KK-T and 78P058KK-T Only) With the µ PD78P054KK-T or 78P058KK-T, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the ...
Page 561 - CHAPTER 27 INSTRUCTION SET; This chapter describes each instruction set of the
561 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µ PD78054 and 78054Y subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series User’s Manual, Instruction (U12326E).”
Page 562 - CHAPTER 27 INSTRUCTION SET; Legends Used in Operation List; Operand identifiers and description methods
562 CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications ...
Page 563 - Description of “operation” column
563 CHAPTER 27 INSTRUCTION SET 27.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL ...
Page 564 - When an area except the internal high-speed RAM area is accessed.; ) selected by the processor clock; This clock cycle applies to internal ROM program.; MOV
564 CHAPTER 27 INSTRUCTION SET 27.2 Operation List Clock Flag Note 1 Note 2 Z AC CY r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 1 2 – A ← r r, A Note 3 1 2 – r ← A A, saddr 2 4 5 A ← (saddr) saddr, A 2 4 5 (saddr) ← A A, sfr 2 – 5 A ← sfr sfr, A ...
Page 565 - ADD
565 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX MOVW AX, sfrp 2 – 8 AX ← sfrp sfrp, AX 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← ...
Page 566 - SUB
566 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A, CY ← A – byte × × × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte × × × A, r Note 3 2 4 – A, CY ← A – r × × × r, A 2 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9 + n A, CY ← A – (...
Page 567 - OR
567 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A ← A ∨ byte × saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte × A, r Note 3 2 4 – A ← A ∨ r × r, A 2 4 – r ← r ∨ A × A, saddr 2 4 5 A ← A ∨ (saddr) × A, !addr16 3 8 9 + n A ← A ∨ (addr16) × A, [HL] 1 4 5 + n A ← A ∨ (HL) × A...
Page 572 - Instructions Listed by Addressing Type
572 CHAPTER 27 INSTRUCTION SET 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Page 577 - Table A-1 shows the major differences between the
577 APPENDIX A DIFFERENCES BETWEEN µ PD78054, 78054Y SUBSERIES AND µ PD78058F, 78058FY SUBSERIES Table A-1 shows the major differences between the µ PD78054, 78054Y Subseries and µ PD78058F, 78058FY Subseries.
Page 578 - APPENDIX A DIFFERENCES BETWEEN; PROM version only
578 APPENDIX A DIFFERENCES BETWEEN µ PD78054, 78054Y SUBSERIES AND µ PD78058F, 78058FY SUBSERIES Table A-1. Major differences between µ PD78054, 78054Y Subseries and µ PD78058F, 78058FY Subseries Part Number µ PD78054, 78054Y Subseries µ PD78058F, 78058FY Subseries Item EMI noise measure None Provid...
Page 579 - APPENDIX B DEVELOPMENT TOOLS; Figure B-1 shows the configuration of the development tools.
579 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78054 and 78054Y subseries. Figure B-1 shows the configuration of the development tools.
Page 580 - APPENDIX B DEVELOPMENT TOOLS
580 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS PROM programming tool • PG-1500 controller Language processing software • Assembler package• C compiler package• C library source file• Device file Debugging tool • System ...
Page 582 - B.1 Language Processing Software
582 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process. Provided with functions to automatically perform generation of symbol table, optimizing processing of b...
Page 584 - B.2 PROM Writing Tools
584 APPENDIX B DEVELOPMENT TOOLS PG-1500 PROM Programmer PA-78P054GC PA-78P054GK PA-78P054KK-T PROM Programmer Adapter A PROM programmer that, by connecting the attached board and separately available PROM programmer adapter, is capable of programming single- chip microcomputers incorporating a PROM...
Page 586 - Notes 1. Under development
586 APPENDIX B DEVELOPMENT TOOLS An in-circuit emulator to debug hardware and software when developing application systems that use the 78K/0 Series. Supports integrated debugger (ID78K0). Used in combination with an interface adapter to connect to an emulation probe and the host machine. An adapter...
Page 590 - I T E M
590 APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawing (For Reference Only) A F D 1 No.1 pin index E EV-9200GC-80 B C M N O L K S R Q P I H J G EV-9200GC-80-G0 I T E M M I L L I M E T E R S I N C H E S A B C D E F G H I J K L M O ...
Page 592 - I J J J; Note Product by TOKYO ELETECH CORPORATION.
592 APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawing (For Reference) (unit: mm) I T E M M I L L I M E T E R S I N C H E S b 0 . 2 5 0 . 0 1 0 c 5 . 3 0 . 2 0 9 a 0.5x19=9.5±0.10 0.020x0.748=0.374±0.004 d 5 . 3 0 . 2 0 9 h 1 . 8 5 ± 0 . 2 0 . 0 7 ...
Page 593 - APPENDIX C EMBEDDED SOFTWARE;
593 APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µ PD78054, 78054Y Subseries, the following embedded software is available. Real-time OS (1/2) RX78K/0 A real-time OS conforming to µ ITRON specifications. Real-time OS Added with the tool (configurator) to crea...
Page 594 - APPENDIX C REGISTER INDEX
594 APPENDIX C REGISTER INDEX Real-time OS (2/2) MX78K0 A µ ITRON specification subset OS. Added with MX78K0 nucleus. OS Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one ex...
Page 595 - APPENDIX D REGISTER INDEX
595 APPENDIX D REGISTER INDEX D.1 Register Index 8-bit timer mode control register (TMC1) .......................................................................................................... 225 8-bit timer output control register (TOC1) ...........................................................
Page 596 - APPENDIX D REGISTER INDEX
596 APPENDIX D REGISTER INDEX [I] IF0H: Interrupt request flag register 0H ................................................................................................... 489 IF0L: Interrupt request flag register 0L ...................................................................................
Page 599 - APPENDIX E REVISION HISTORY; Major revisions by edition and revised chapters are shown below.
599 APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version Revised Chapters 2nd P40/AD0-P47/AD7 pin I/O circuit types were changed. CHAPTER 2 Pin Functions Connection method of unused AV REF1 pin was changed. Caution...
Page 603 - Thank you for your kind support.; Document Rating; Name; Facsimile
Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily accept thaterrors may occur. Despite all the care andp r e c a u t i o n s w e ' v e t a k e n , y o u m a yencounter problems in the documentation.Pleas...
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Manual
NEC PD75402A
Manual
NEC NP-V311X
Manual
NEC LT240K, LT260K
Manual
NEC DTR-IR-2
Manual
NEC j
Manual
NEC 0724-20
Manual