NEC PD75402A - Manual

NEC PD75402A

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Table of Contents:

  • Page 6 – CONTENTS; DIFFERENCES BETWEEN
  • Page 7 – Differences Between
  • Page 9 – Change of
  • Page 11 – CONTENTS OF TABLES; Title
  • Page 12 – Remarks
  • Page 13 – OUTLINE OF FUNCTIONS
  • Page 14 – Standard
  • Page 15 – Table 1-1 shows the differences between the; Table 1-1 Differences Between; The
  • Page 16 – BLOCK DIAGRAM; Parentheses for the
  • Page 17 – RESET
  • Page 18 – PROM mode; CE; : Program power supply
  • Page 19 – Normal operating mode; is to be set to the GND potential.
  • Page 21 – CHAPTER 2. PIN FUNCTIONS; pin level as shown in the table below.; Operating Mode
  • Page 22 – In the; For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”.
  • Page 23 – If using the
  • Page 24 – Pin Port 1; NORMAL OPERATING MODE; P10 can be built in with the pull-up resistor.
  • Page 26 – It is also possible to supply the clock from the exterior.; A positive power supply pin.
  • Page 28 – PIN INPUT/OUTPUT CIRCUITS; Pin; A circle
  • Page 29 – Type B
  • Page 30 – data
  • Page 31 – UNUSED PIN TREATMENT
  • Page 32 – CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP; DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
  • Page 40 – IE
  • Page 42 – The program counter operates as follows.; CHAPTER 4. INTERNAL CPU FUNCTIONS
  • Page 44 – Data Memory
  • Page 46 – as a register or not.
  • Page 47 – CY
  • Page 48 – Address
  • Page 50 – shows its configuration.; Fig. 4-10 Program Status Word Configuration; IST0 turns 0 and SK0 to SK2 and CY turn indeterminate at RESET input.; Table 4-1 Carry Flag Manipulation Instructions; Skip Flag
  • Page 52 – CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS; DIGITAL INPUT/OUTPUT PORTS; Note
  • Page 53 – Port; LED direct drive capability
  • Page 55 – Input Buffer
  • Page 57 – units by PMGB for ports 2 and 5, and by PMGA for port 6.
  • Page 58 – As all the input/output ports in the
  • Page 62 – Table 5-4 Internal Pull-Up Resistor Specification for Each Port; PD75P402, pull-up resistors cannot be incorporated into port 5.
  • Page 65 – Selector
  • Page 66 – Example
  • Page 68 – Long connection circuit wiring; PORTn
  • Page 69 – Signal line close to varyin high current; Signal is picked up.
  • Page 71 – As the PCC is set in 0 by RESET input,; Table 5-5 Maximum Time Required for Change of CPU Clock; PCC Before Change; When standby mode is not set until; after Power-On Reset; RESET Input Signal
  • Page 73 – PD75402 is shown below. Setting of bit 1 of the PCC is; PD75402 Processor Clock Control Register Format
  • Page 74 – The configuration of the clock output circuit is shown in Fig. 5-18.; Fig. 5-18 Clock Output Circuit Configuration; that a short pulse is not output.
  • Page 75 – CLOM is a 4-bit register used to control clock output.; Fig. 5-19 Clock Output Mode Register Format
  • Page 77 – Basic Interval Timer Configuration; The configuration of the basic interval timer is shown in Fig. 5-21.; Fig. 5-21 Basic Interval Timer Configuration; Instruction execution
  • Page 78 – MOV; Fig. 5-22 Basic Interval Timer Mode Register Format
  • Page 80 – Module 1
  • Page 81 – Operation-halted mode; Serial data transfer is performed MSB-first.
  • Page 82 – This mode conforms to the NEC serial bus format.; Fig. 5-23 Example of SBI System Configuration
  • Page 84 – Selects the serial clock to be used.; Serial clock counter; transmission/reception has been performed.
  • Page 85 – • In SBI mode; Serial clock control circuit; the internal system clock is used.; Register Functions; by bit using the individual bit names.
  • Page 86 – Serial interface operating mode selection bit (W)
  • Page 92 – A serial transfer is started by writing data to SIO.; Fig. 5-27 Configuration Around Shift Register; been written into the shift register.
  • Page 95 – The P01/SCK pin status depends on the CSIM1 setting as shown below.; Register setting; • Serial bus interface control register (SBIC)
  • Page 96 – Reset input clears the CSIM register to 00H.; Read only
  • Page 98 – SBIC is manipulated by bit manipulation instructions.; Command trigger bit; Write only
  • Page 99 – bit by bit in synchronization with the serial clock.
  • Page 100 – following clocks can be selected.; Signals
  • Page 101 – Start of transfer
  • Page 104 – OR state. The serial data bus line requires a pull-up resistor.; Fig. 5-32 Example of SBI Serial Bus System Configuration
  • Page 105 – software is very large.; Address/command/data differentiation function; Identifies serial data as an address, command or actual data.
  • Page 106 – the configuration shown below.; Address Transfer
  • Page 107 – hardware to detect the bus release signal.; Slave incorporate hardware to detect the command signal.
  • Page 108 – disconnect directive is received from the master.
  • Page 109 – by address transmission.; communication specifications.
  • Page 110 – not to have been performed correctly.
  • Page 111 – master automatically terminates output of the SCK serial clock.
  • Page 116 – Disablin of automatic busy signal output; Serial clock selection
  • Page 129 – XCH
  • Page 130 – Serial bus configuration; Slave CPU
  • Page 132 – READ command; is interpreted as a 256-byte data transfer specification.
  • Page 133 – the slave that all the data has been correctly transferred.
  • Page 134 – The format of the status byte returned by the slave is shown below.
  • Page 136 – Error Data
  • Page 137 – CHAPTER 6. INTERRUPT FUNCTIONS; On the; INTERRUPT CONTROL CIRCUIT CONFIGURATION
  • Page 140 – INTERRUPT CONTROL CIRCUIT HARDWARE; Interrupt request flag & interrupt enable flag
  • Page 141 – Therefore, pulses narrower than the width of the 2 cycles (2t; ) of sampling clock are eliminated as noise,
  • Page 142 – must be of sufficient width to avoid being eliminated as noise.
  • Page 143 – IME is manipulated by the EI/DI instructions.
  • Page 144 – in multiple interrupt.; Table 6-3 IST0 Interrupt Servicing Status
  • Page 146 – routine program are as shown below.
  • Page 147 – D: Execution of interrupt routine; performed following the instruction being executed.
  • Page 149 – All interrupts disabled and status 0 set by RESET input.
  • Page 150 – Same as
  • Page 152 – CHAPTER 7. STANDBY FUNCTION; STOP mode; HALT mode
  • Page 153 – Operation state; and HALT instruction set bits 3 and 2 of the PCC respectively.)
  • Page 154 – instruction execution begins.
  • Page 155 – HALT mode reset by interrupt generation
  • Page 156 – The interrupt request flag is held.; STANDBY MODE APPLICATION; When using the standby mode, proceed as follows:
  • Page 157 – CHAPTER 8. RESET FUNCTION
  • Page 159 – CHAPTER 9. INSTRUCTION SET; ARCHITECTURE AND MEMORY MAP”.
  • Page 163 – FF0H to FFFH; MB is the accessible memory bank.; Description of machine cycle field; The value of S changes as follows:; Data memory
  • Page 164 – Move instructions
  • Page 165 – Branch
  • Page 167 – Dn : Immediate data for mem; Bit manipulation addressing operation code; Bn : Immediate data for bit address (0 to 3) described at bit
  • Page 168 – Arithmetic and
  • Page 169 – Memory bit manipulation instructions
  • Page 173 – Program Memory; For instance, when there is a MOVT XA, @PCXA instruction at position
  • Page 174 – to I
  • Page 175 – the result into the A register.
  • Page 176 – RORC A; An to A; NOT A
  • Page 177 – INCS reg; of incrementing, skips the next instruction.; INCS mem; to D; DECS reg; of decrementing, skips the next instruction.
  • Page 179 – SET1 CY; Clears the carry flag.; SKT CY; When the carry flag is 1, skips the next instruction.; NOT1 CY
  • Page 182 – BR addr
  • Page 183 – RET
  • Page 184 – PUSH rp; rp; POP rp
  • Page 185 – EI; determined by each interrupt enable flag.; EI IEXXX; DI; to N
  • Page 187 – STOP; NOP
  • Page 188 – following instructions not available with the
  • Page 189 – APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY
  • Page 190 – Language Processor; PROM Writing Tools; Hardware; and operating systems quoted above.
  • Page 191 – APPENDIX B. DEVELOPMENT TOOLS; Debugging Tools; Their respective system configurations are as follows.; Maintenance product
  • Page 192 – Development Tool Configuration; PROM Programmer
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USER'S MANUAL

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PD75402A

4-BIT SINGLE-CHIP MICROCOMPUTER

µ

PD75402A

µ

PD75P402

Document No. IEU1270C

(O. D. No. IEU-644D)

Date Published March 1994 P
Printed in Japan

© NEC Corporation 1989

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Summary

Page 6 - CONTENTS; DIFFERENCES BETWEEN

- i - CONTENTS CHAPTER 1. GENERAL ............................................................................................................................... 1 1.1 OUTLINE OF FUNCTIONS . ................................................................................................................

Page 7 - Differences Between

- ii - CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 31 4.1 PROGRAM COUNTER (PC) ........................................................................................................................... 31 4.2 PROGRAM ...

Page 9 - Change of

- iv - CONTENTS OF FIGURES Fig. No Title Page 3-1 Static RAM Address Updating Method ............................................................................................. 25 4-1 Program Counter Configuration .......................................................................................

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