Page 3 - EEPROM is a trademark of NEC Electronics Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
3 User’s Manual U10676EJ3V0UM EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. T...
Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .
4 User’s Manual U10676EJ3V0UM These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country.Diversion contrary to the law of that country is prohibited. T h e i n f o r m a t i o n i n t h i s d o c u m e n t i s c u r r...
Page 5 - Regional Information; Device availability; NEC Electronics Hong Kong Ltd.
5 User’s Manual U10676EJ3V0UM Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power ...
Page 6 - Major Revisions in This Edition; and INTT2 have lower priority); The mark
6 User’s Manual U10676EJ3V0UM Major Revisions in This Edition Pages Description p.210 Correction of description in figure in 7.9 Application of Interrupt (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) p....
Page 7 - INTRODUCTION
7 User’s Manual U10676EJ3V0UM INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µ PD754144 and 754244 and design application systems using these microcontrollers. Purpose This manual is intended to give users an understanding of the hardware ...
Page 8 - Related Documents; However, preliminary versions are not marked as such.; Documents related to devices
8 User’s Manual U10676EJ3V0UM Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to devices Document Name Document No. µ PD754144, 754244 Data Sheet U10040E µ PD754144, 754244...
Page 9 - AV
9 User’s Manual U10676EJ3V0UM TABLE OF CONTENTS CHAPTER 1 GENERAL ..................................................................................................................... 17 1.1 Functional Outline .............................................................................................
Page 16 - LIST OF TABLES; Title
16 User’s Manual U10676EJ3V0UM LIST OF TABLES Table No. Title Page 2-1 Pin Functions of Digital I/O Por ts ....................................................................................................... 24 2-2 Functions of Non-Por t Pins .........................................................
Page 17 - CHAPTER 1 GENERAL; APPLICATIONS
17 User’s Manual U10676EJ3V0UM CHAPTER 1 GENERAL The µ PD754144 and 754244 are 4-bit single-chip microcontrollers in the NEC 75XL Series, the successor to the 75X Series that boasts a wealth of variations. The µ PD754144 and 754244 have extended CPU functions compared to the µ PD75048, a 75X Series ...
Page 18 - CHAPTER 1 GENERAL; Functional Outline
CHAPTER 1 GENERAL 18 User’s Manual U10676EJ3V0UM 1.1 Functional Outline Item µ PD754144 µ PD754244 Instruction execution time • 4, 8, 16, 64 µ s (at f CC = 1.0 MHz) • 0.95, 1.91, 3.81, 15.3 µ s (at f X = 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µ s (at f X = 6.00 MHz) On-chip Mask ROM 4096 × 8 bits (0000H...
Page 19 - Ordering Information; Part Number; Remark; indicates ROM code suffix.; Differences Between Series Products
CHAPTER 1 GENERAL 19 User’s Manual U10676EJ3V0UM 1.2 Ordering Information Part Number Package µ PD754141GS- ××× -BA5 20-pin plastic SOP (7.62 mm (300)) µ PD754141GS- ××× -GJG 20-pin plastic SSOP (7.62 mm (300)) µ PD754244GS- ××× -BA5 20-pin plastic SOP (7.62 mm (300)) µ PD754244GS- ××× -GJG 20-pin p...
Page 21 - Pin configuration of; IC: Internally Connected (Directly connect to V
CHAPTER 1 GENERAL 21 User’s Manual U10676EJ3V0UM 1.5 Pin Configuration (Top View) • Pin configuration of µ PD754144 • 20-pin plastic SOP (7.62 mm (300)) µ PD754144GS- ××× -BA5 • 20-pin plastic SSOP (7.62 mm (300)) µ PD754144GS- ××× -GJG 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESET CL1 CL...
Page 23 - Pin Name
CHAPTER 1 GENERAL 23 User’s Manual U10676EJ3V0UM Pin Name P30 to P33: Port 3 P60 to P63: Port 6 P70 to P73: Port 7 P80: Port 8 KR4 to KR7: Key return 4 to 7 INT0: External vectored interrupt 0 PTH00, PTH01: Programmable threshold port analog input 0, 1 PTO0 to PTO2: Programmable timer output 0 to 2 ...
Page 24 - Circled characters indicate Schmitt-triggered input.
24 User’s Manual U10676EJ3V0UM CHAPTER 2 PIN FUNCTIONS 2.1 Pin Functions of µ PD754244 Table 2-1. Pin Functions of Digital I/O Ports Pin Name I/O Alternate Function 8-Bit After Reset I/O Circuit Function I/O Type Note 1 P30 I/O PTO0 × Input E-B P31 PTO1 P32 PTO2 P33 – P60 I/O AV REF × Input F -A P61...
Page 25 - CHAPTER 2 PIN FUNCTIONS; Note; Circled characters indicate Schmitt triggered input.
CHAPTER 2 PIN FUNCTIONS 25 User’s Manual U10676EJ3V0UM Table 2-2. Functions of Non-Port Pins Pin Name I/O Alternate Function After Reset I/O Circuit Function Type Note PTO0 Output P30 Timer counter output pins. Input E-B PTO1 P31 PTO2 P32 INT0 Input P61 Edge-detected vectored interrupt input Input F...
Page 26 - Description of Pin Functions; Port 6: Programmable threshold port reference voltage input (AV; Generation of the RESET signal sets the input mode.
CHAPTER 2 PIN FUNCTIONS 26 User’s Manual U10676EJ3V0UM 2.2 Description of Pin Functions 2.2.1 P30 to P33 (Port 3) ... I/O pins shared with PTO0 to PTO2 P60 to P63 (Port 6) ... I/O pins shared with AV REF , INT0, PTH00, PTH01 P80 (Port 8) ... I/O pin These are 4-bit I/O ports with output latches (por...
Page 27 - (c) Active at both rising and falling edges
CHAPTER 2 PIN FUNCTIONS 27 User’s Manual U10676EJ3V0UM 2.2.4 INT0 ... input pin shared with port 6 This pin inputs the vectored interrupt signal detected by the edge. A noise eliminator is selectable for INT0. The edge to be detected can be specified by using the edge detection mode register (IM0). ...
Page 28 - No external clock can be input.; RC oscillation; An external clock can also be input to these pins.
CHAPTER 2 PIN FUNCTIONS 28 User’s Manual U10676EJ3V0UM 2.2.8 AV REF ... input pin shared with port 6 This is a reference voltage input pin. An analog reference voltage for the programmable threshold port is input. 2.2.9 CL1 and CL2 ( µ PD754144 only) These pins are used to connect the RC oscillator ...
Page 30 - The following diagrams show the I/O circuits of the pins of the
CHAPTER 2 PIN FUNCTIONS 30 User’s Manual U10676EJ3V0UM 2.3 Pin I/O Circuits The following diagrams show the I/O circuits of the pins of the µ PD754244. Note that in these diagrams the I/ O circuits have been slightly simplified. Type A Type B Type D Type E-B Type B-A Type F-A V DD IN P-ch N-ch Data ...
Page 31 - Processing of Unused Pins; Table 2-3. Recommended Connection of Unused Pins
CHAPTER 2 PIN FUNCTIONS 31 User’s Manual U10676EJ3V0UM 2.4 Processing of Unused Pins Table 2-3. Recommended Connection of Unused Pins Pin Recommended Connection P30/PTO0 Input: Independently connect to V SS or V DD via a resistor. P31/PTO1 Output: Leave open. P32/PTO2 P33 P60/AV REF P61/INT0 P62/PTH...
Page 33 - CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 33 User’s Manual U10676EJ3V0UM Figure 3-1. Selecting MBE = 0 Mode and MBE = 1 Mode Internal hardware and static RAM manipulation repeated. ; MBE = 0 by vector table <Main program> SET 1 MBE CLR 1 MBE MBE = 1 MBE = 0 SET 1 MBE MBE = 1 <Subrou...
Page 34 - Example
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 34 User’s Manual U10676EJ3V0UM 3.1.2 Addressing mode of data memory The 75XL architecture employed for the µ PD754244 provides the seven types of addressing modes shown in Table 3-1. This means that the data memory space can be efficiently addressed ...
Page 39 - Figure 3-3. Updating Address of Static RAM
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 39 User’s Manual U10676EJ3V0UM Figure 3-3. Updating Address of Static RAM 0XH FXH @DL 4-bit transfer DECS D INCS D DECS L INCS L @HL 4-bit manipulation 8-bit manipuIation DECS H INCS H DECS L INCS L Auto decrement Auto increment DECS HL INCS HL Direc...
Page 45 - Bank Configuration of General-Purpose Registers; Table 3-2. Register Bank Selected by RBE and RBS
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 45 User’s Manual U10676EJ3V0UM RBE Register Bank Fixed to 0 Remark × = don’t care RBE is automatically saved or restored during subroutine processing and therefore can be set while subroutine processing is under execution. When interrupt servicing is...
Page 46 - Figure 3-4. Example of Using Register Banks
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 46 User’s Manual U10676EJ3V0UM Figure 3-4. Example of Using Register Banks <Main program> <Single interrupt> <Nesting of two interrupts> ; RBE = 1 <Nesting of three interrupts> ; RBE = 0 ; RBE = 0 in vector table in vector tab...
Page 56 - These are not registered as reserved words.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 56 User’s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (5/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated manipulation Remarks b3 b2 b1 b0 1-bit 4-bit 8-bit addressing FC0H Bit sequential buffer 0 (BSB0) R/W me...
Page 60 - Difference between MkI and MkII modes; The CPU of the; Table 4-1. Differences Between MkI and MkII Modes
60 User’s Manual U10676EJ3V0UM CHAPTER 4 INTERNAL CPU FUNCTION 4.1 Function to Select MkI and MkII Modes 4.1.1 Difference between MkI and MkII modes The CPU of the µ PD754244 has two modes to be selected: MkI and MkII. These modes can be selected by using bit 3 of the stack bank select register (SBS...
Page 61 - CHAPTER 4 INTERNAL CPU FUNCTION; Figure 4-1. Format of Stack Bank Select Register; Specifies stack area
CHAPTER 4 INTERNAL CPU FUNCTION 61 User’s Manual U10676EJ3V0UM 4.1.2 Setting stack bank select register (SBS) The MkI mode or MkII mode is selected by using the stack bank select register (SBS). Figure 4-1 shows the format of this register. The stack bank select register is set by using a 4-bit memo...
Page 62 - Figure 4-2. Configuration of Program Counter; each time that instruction has been executed.
CHAPTER 4 INTERNAL CPU FUNCTION 62 User’s Manual U10676EJ3V0UM 4.2 Program Counter (PC) ··· 12 bits This is a binary counter that holds an address of the program memory. Figure 4-2. Configuration of Program Counter PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The value of the program counter (P...
Page 63 - bits; program memory addresses.; used to decrease the number of program steps (refer to
CHAPTER 4 INTERNAL CPU FUNCTION 63 User’s Manual U10676EJ3V0UM 4.3 Program Memory (ROM) ··· 4096 × 8 bits The program memory stores a program, interrupt vector table, the reference table of the GETI instruction, and table data. The program memory is addressed by the program counter. The table data c...
Page 64 - Can be used in the MkII mode only.; by means of a BR PCDE or BR PCXA instruction.
CHAPTER 4 INTERNAL CPU FUNCTION 64 User’s Manual U10676EJ3V0UM Figure 4-3. Program Memory Map 7 6 0 MBE RBE Internal reset start address (higher 4 bits) Internal reset start address (lower 8 bits) MBE RBE INTBT start address (higher 4 bits) INTBT start address (lower 8 bits) MBE RBE INT0 start addre...
Page 65 - bits; General-purpose register area
CHAPTER 4 INTERNAL CPU FUNCTION 65 User’s Manual U10676EJ3V0UM 4.4 Data Memory (RAM) ... 128 words × 4 bits The data memory consists of data areas and a peripheral hardware area as shown in Figure 4-4. The data memory consists the following banks with each bank made up of 256 words × 4 bits. • Memor...
Page 66 - the bank are specified by 8-bit immediate data or a register pair.; Bank Configuration of Data Memory and
CHAPTER 4 INTERNAL CPU FUNCTION 66 User’s Manual U10676EJ3V0UM 4.4.2 Specifying bank of data memory A memory bank is specified by a 4-bit memory bank select register (MBS) when bank specification is enabled by setting a memory bank enable flag (MBE) to 1 (MBS = 0, 4, or 15). When bank specification ...
Page 69 - Configuration of General-Purpose Registers; whether the registers in this area are used or not.; Figure 4-6. Configuration of Register Pair
CHAPTER 4 INTERNAL CPU FUNCTION 69 User’s Manual U10676EJ3V0UM 0 3 B 0 3 C 0 3 D 0 3 E 0 3 H 0 3 L 0 3 X 0 3 A One bank 000H 001H 002H 003H 004H 005H 006H 007H 008H 00FH 010H 017H018H . . . . . 01FH Same configura- tion as bank 0 Same configura- tion as bank 0 Same configura- tion as bank 0 Register...
Page 71 - Example of SP initialization
CHAPTER 4 INTERNAL CPU FUNCTION 71 User’s Manual U10676EJ3V0UM When 00H is set to SP as the initial value, memory bank 0 specified by SBS is used as the stack area, starting from the highest address (07FH). The stack area can be used only in memory bank 0. If stack operation is performed from addres...
Page 73 - The contents of PSW other than MBE and RBE are not saved or restored.
CHAPTER 4 INTERNAL CPU FUNCTION 73 User’s Manual U10676EJ3V0UM Figure 4-11. Data Saved to Stack Memory (MkII Mode) Stack SP – 1 SP PUSH instruction Stack PC11-PC8 PC3-PC0 PC7-PC4 CALL, CALLA, CALLF instruction Stack Interrupt SP – 4 SP – 3 SP – 2 SP – 5 PC11-PC8 PC3-PC0 PC7-PC4 SP – 2 SP – 1 SP SP –...
Page 74 - Figure 4-13. Configuration of Program Status Word
CHAPTER 4 INTERNAL CPU FUNCTION 74 User’s Manual U10676EJ3V0UM 4.8 Program Status Word (PSW) ... 8 Bits The program status word (PSW) consists of flags closely related to the operations of the processor. PSW is mapped to addresses FB0H and FB1H of the data memory space, and the 4 bits of address FB0...
Page 75 - Table 4-4. Carry Flag Manipulation Instruction
CHAPTER 4 INTERNAL CPU FUNCTION 75 User’s Manual U10676EJ3V0UM Table 4-4. Carry Flag Manipulation Instruction Instruction (Mnemonic) Operation and Processing of Carry Flag Carry flag manipulation SET1 CY Sets CY to 1 instruction CLR1 CY Clears CY to 0 NOT1 CY Inverts content of CY SKT CY Skips if co...
Page 76 - IST0, and Interrupt Servicing
CHAPTER 4 INTERNAL CPU FUNCTION 76 User’s Manual U10676EJ3V0UM (3) Interrupt status flags (IST1 and IST0) The interrupt status flags record the status of the processing under execution (for details, refer to Table 7-3 IST, IST0, and Interrupt Servicing ). Table 4-5. Contents of Interrupt Status Flag...
Page 77 - RBE is automatically initialized.
CHAPTER 4 INTERNAL CPU FUNCTION 77 User’s Manual U10676EJ3V0UM (5) Register bank enable flag (RBE) This flag specifies whether the register bank of the general-purpose registers is expanded or not. RBE can be set or reset at any time by using a bit manipulation instruction, regardless of the setting...
Page 78 - Figure 4-14. Configuration of Bank Select Register
CHAPTER 4 INTERNAL CPU FUNCTION 78 User’s Manual U10676EJ3V0UM 4.9 Bank Select Register (BS) The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS) which specify the register bank and the memory bank to be used, respectively. RBS and M...
Page 80 - lation instructions
80 User’s Manual U10676EJ3V0UM CHAPTER 5 EEPROM The µ PD754244 incorporates not only a 128-word × 4-bit static RAM but also a 16-word × 8-bit EEPROM (Electrically Erasable PROM) as data memory. EEPROM, unlike static RAM, can retain its contents when the power is turned off. Unlike EPROM, contents ca...
Page 81 - CHAPTER 5 EEPROM; Figure 5-1. Format of EEPROM Write Control Register; EEPROM read enable flag
CHAPTER 5 EEPROM 81 User’s Manual U10676EJ3V0UM 5.3 EEPROM Write Control Register (EWC) The EEPROM write control register (EWC) is an 8-bit register used to control manipulation of EEPROM. Figure 5-1 shows its configuration. Figure 5-1. Format of EEPROM Write Control Register ERE 7 EWTC6 6 EWTC5 5 E...
Page 82 - Interrupt Related to EEPROM Control
CHAPTER 5 EEPROM 82 User’s Manual U10676EJ3V0UM Cautions 1. The write time depends on the system clock oscillation frequency. 2. Set EWTC4-EWTC6 so that the write time is as follows. With µ PD754144 ··· 18 × 2 8 /f CC (4.6 ms: f CC = 1.0 MHz) With µ PD754244 ··· 4.0 ms MIN., 10.0 ms MAX. Clear EWE t...
Page 83 - EEPROM Manipulation Method
CHAPTER 5 EEPROM 83 User’s Manual U10676EJ3V0UM 5.5 EEPROM Manipulation Method 5.5.1 EEPROM manipulation instructions Instructions that can be used to manipulate the EEPROM are shown below, divided into read instructions and write instructions. (1) Read manipulation instructions Instruction Group Mn...
Page 85 - Use the following procedure to write to EEPROM.; Operating mode selection bit
CHAPTER 5 EEPROM 85 User’s Manual U10676EJ3V0UM 5.5.3 Write manipulation Use the following procedure to write to EEPROM. Any instruction other than one related to EEPROM writing can be executed even during an EEPROM write operation. EWST, EWTC and EWE can be set simultaneously by an 8-bit memory man...
Page 87 - Cautions on EEPROM Writing; Cautions on EEPROM writing are shown below.
CHAPTER 5 EEPROM 87 User’s Manual U10676EJ3V0UM 5.6 Cautions on EEPROM Writing Cautions on EEPROM writing are shown below. Be sure to read these before writing to EEPROM. Cautions 1. Before writing, make sure that EWST is 0. While EEPROM is being written, if a write instruction is executed again, th...
Page 88 - CHAPTER 6 PERIPHERAL HARDWARE FUNCTION; Figure 6-1. Data Memory Address of Digital Ports
88 User’s Manual U10676EJ3V0UM CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Ports The µ PD754244 uses memory mapped I/O, and all the I/O ports are mapped to the data memory space. Figure 6-1. Data Memory Address of Digital Ports FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H P33 P63 P73 – Ad...
Page 89 - CHAPTER 6 PERIPHERAL HARDWARE FUNCTION; Table 6-1. Types and Features of Digital Ports; Port; Hardware Controlling Interrupt Function; are turned off, and the ports are set to the input mode.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 89 User’s Manual U10676EJ3V0UM 6.1.1 Types, features, and configurations of digital I/O ports Table 6-1 shows the types of digital I/O ports. Figures 6-2 to 6-9 show the configuration of each port. Table 6-1. Types and Features of Digital Ports Port Function Op...
Page 94 - when the corresponding register bit is “1”.; MBE
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 94 User’s Manual U10676EJ3V0UM 6.1.2 Setting I/O mode The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 6- 10. Ports 3 and 6 can be set to the input or output mode in 1-bit units by using port mode regis...
Page 95 - Figure 6-10. Format of Each Port Mode Register; Specification; Port mode register group A
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 95 User’s Manual U10676EJ3V0UM Figure 6-10. Format of Each Port Mode Register Specification 0 Input mode (output buffer off) 1 Output mode (output buffer on) Port mode register group A 7 6 5 4 3 2 1 0 PM30 PM31 PM33 PM32 PM60 PM61 PM62 PM63 Address PMGA FE8H Sy...
Page 98 - the data of each pin is manipulated.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 98 User’s Manual U10676EJ3V0UM 6.1.4 Operation of digital I/O port The operations of each port and port pin when a data memory manipulation instruction is executed to manipulate a digital I/O port differ depending on whether the port is set to the input or outp...
Page 100 - Figure 6-11. Format of Pull-up Resistor Specification Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 100 User’s Manual U10676EJ3V0UM 6.1.5 Connecting pull-up resistor Each port pin of the µ PD754244 can be connected to a pull-up resistor. Some pins can be connected to a pull- up resistor via software and others can be connected by a mask option. Table 6-4 show...
Page 101 - the data of the output latch is loaded to the internal bus.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 101 User’s Manual U10676EJ3V0UM 6.1.6 I/O timing of digital I/O port Figure 6-12 shows the timing at which data is output to the output latch and the timing at which the pin data or the data of the output latch is loaded to the internal bus. Figure 6-13 shows t...
Page 103 - Figure 6-14 shows the configuration of the clock generator.; Instruction execution; : System clock frequency; ) of the CPU clock is equal to one machine cycle of the instruction.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 103 User’s Manual U10676EJ3V0UM 6.2 Clock Generator The clock generator supplies various clocks to the CPU and peripheral hardware units and controls the operation mode of the CPU. 6.2.1 Configuration of clock generator Figure 6-14 shows the configuration of th...
Page 105 - Function and operation of clock generator
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 105 User’s Manual U10676EJ3V0UM 6.2.2 Function and operation of clock generator The clock generator generates the following types of clocks and controls the operation mode of the CPU in the standby mode. • System clock f X • CPU clock Φ • Clock to peripheral ha...
Page 106 - CHAPTER 8 STANDBY FUNCTION
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 106 User’s Manual U10676EJ3V0UM (1) Processor clock control register (PCC) PCC is a 4-bit register that selects the CPU clock Φ with the lower 2 bits and controls the CPU operation mode with the higher 2 bits (refer to Figure 6-15 ). When either bit 3 or 2 of t...
Page 107 - Figure 6-15. Format of Processor Clock Control Register; CPU operating mode control bits; and f
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 107 User’s Manual U10676EJ3V0UM Figure 6-15. Format of Processor Clock Control Register PCC3 3 2 1 0 FB3H Address PCC Symbol PCC2 PCC1 PCC0 CPU operating mode control bits PCC3 PCC2 Operating mode 0 0 Normal operating mode 0 1 HALT mode 1 0 STOP mode 1 1 Settin...
Page 108 - An external clock cannot be input for RC oscillation.; Cautions f; Figure 6-16. RC Oscillation External Circuit; An external clock can also be input.; Crystal/ceramic oscillation
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 108 User’s Manual U10676EJ3V0UM X1 X2V SS Crystal or ceramic resonator PD754244 µ X1 X2 Externalclock PD754244 µ (2) System clock oscillator (a) µ PD754144 (RC oscillation) The system clock oscillator oscillates by means of a resistor (R) and capacitor (C) conn...
Page 109 - Figure 6-18 shows incorrect examples of connecting the resonator.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 109 User’s Manual U10676EJ3V0UM Cautions 1. The X2 pin of the µ PD754244 is internally pulled up to V DD by a resistor of 50 k Ω (typ.) in the STOP mode. 2. Wire the portion enclosed by the dotted lines in Figures 6-16 and 6-17 as follows to prevent adverse inf...
Page 110 - (c) High alternating current close to signal line
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 110 User’s Manual U10676EJ3V0UM Figure 6-18. Example of Incorrect Resonator Connection (2/3) (b) Crossed signal line µ PD754144 CL1 CL2 V SS PORTn (n = 3, 6-8) µ • PD754144 µ • PD754244 µ PD754244 X1 X2 V SS PORTn (n = 3, 6-8) (c) High alternating current close...
Page 111 - (d) Current flowing through power line of oscillator
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 111 User’s Manual U10676EJ3V0UM Figure 6-18. Example of Incorrect Resonator Connection (3/3) (d) Current flowing through power line of oscillator (potential at points A, B, and C changes) µ PD754144 CL1 CL2 V SS PORTn(n = 3, 6-8) V DD A B High current µ • PD754...
Page 112 - Table 6-5. Maximum Time Required for CPU Clock Switching
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 112 User’s Manual U10676EJ3V0UM 6.2.3 Setting CPU clock (1) Time required to switch CPU clock The CPU clock can be switched by using the lower 2 bits of PCC. The processor does not operate with the selected clock, however, immediately after data has been writte...
Page 113 - Figure 6-19. CPU Clock Switching Example; Notes
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 113 User’s Manual U10676EJ3V0UM Figure 6-19. CPU Clock Switching Example <1> Wait time Note 1 to secure the oscillation stabilization time in response to RESET signal generation. <2> The CPU starts operating at the lowest system clock speed Note 2 ....
Page 114 - Figure 6-20. Block Diagram of Basic Interval Timer/Watchdog Timer
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 114 User’s Manual U10676EJ3V0UM 6.3 Basic Interval Timer/Watchdog Timer The µ PD754244 has an 8-bit basic interval timer/watchdog timer that has the following functions. (a) Interval timer operation to generate reference time interrupt (b) Watchdog timer operat...
Page 116 - Figure 6-21. Format of Basic Interval Timer Mode Register; In the
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 116 User’s Manual U10676EJ3V0UM Figure 6-21. Format of Basic Interval Timer Mode Register Note In the µ PD754244 only, wait time is selectable when standby mode is released. In the µ PD754144, wait time is always fixed to 2 9 /f CC (512 µ s at 1.0 MHz). 3 2 1 0...
Page 117 - To set watchdog timer function
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 117 User’s Manual U10676EJ3V0UM 6.3.3 Watchdog timer enable flag (WDTM) WDTM is a flag that enables assertion of the reset signal when an overflow occurs. This flag is set by a bit manipulation instruction. Once this flag has been set, it cannot be cleared by a...
Page 119 - Initial setting; Figure; indicates occurrence and detection of a program hang-up.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 119 User’s Manual U10676EJ3V0UM Initial setting 6.3.5 Operation as watchdog timer The basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when an overflow occurs in the basic interval timer (BT), if WDTM is se...
Page 120 - To use the; It is 7.81 ms when the
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 120 User’s Manual U10676EJ3V0UM Example To use the µ PD754244 as a watchdog timer with a time interval of 5.46 ms (at f X = 6.0 MHz). Note Divide the program into several modules, each of which is completed within the set time of BTM (5.46 ms), and clear BT at ...
Page 121 - Caution
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 121 User’s Manual U10676EJ3V0UM 6.3.6 Other functions The basic interval timer/watchdog timer has the following functions, regardless of the operations as the basic interval timer or watchdog timer. <1> Selects and counts wait time after standby mode has ...
Page 122 - The; Corresponding function is not available.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 122 User’s Manual U10676EJ3V0UM 6.4 Timer Counter The µ PD754244 incorporates a three-channel timer counter. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) C...
Page 123 - Execution of the instruction; Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 123 User’ s Man ual U10676EJ3V0UM Figure 6-23. Block Diagram of Timer Counter (Channel 0) Note Execution of the instruction Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0. – TM06 TM05 TM04 TM03 TM02 0 0 TM0 8 Internal bus 8 8 Modulo registe...
Page 125 - Caution Be sure to clear bit 7 to 0 when setting data to TC2.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 125 User’ s Man ual U10676EJ3V0UM Figure 6-25. Block Diagram of Timer Counter (Channel 2) Note Execution of the instruction Caution Be sure to clear bit 7 to 0 when setting data to TC2. 8 Internal bus – TM26 TM25 TM24 TM23 TM22 TM21 TM20 From clock generator MP...
Page 126 - SEL; CP = 977 kHz when the
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 126 User’s Manual U10676EJ3V0UM (1) Timer counter mode registers (TM0, TM1, TM2) A timer counter mode register (TMn) is an 8-bit register that controls the corresponding timer counter. Figures 6-26 to 6-28 show the formats of the various mode registers. The tim...
Page 127 - Be sure to clear bits 0 and 1 to 0 when setting data to TM0.; the count pulse set becomes 0 and TM0 does not operate as a timer.; Timer start command bit
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 127 User’s Manual U10676EJ3V0UM Figure 6-26. Format of Timer Counter Mode Register (Channel 0) Note Be sure to clear bits 0 and 1 to 0 when setting data to TM0. Caution After a reset, all bits of TM0 become "0", therefore when operating the timer it is ...
Page 129 - This mode is used as a carrier generator mode when used in; set becomes 0 and TM0 does not operate as a timer.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 129 User’s Manual U10676EJ3V0UM Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (2/2) TM13 Clears counter and IRQT1 flag when "1" is written. Starts count operationif bit 2 is set to "1". Timer start command bit Operation mode TM1...
Page 132 - Figure 6-29. Format of Timer Counter Output Enable Flag
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 132 User’s Manual U10676EJ3V0UM (2) Timer counter output enable flags (TOE0, TOE1) Timer counter output enable flags TOE0 and TOE1 enable or disable output to the PTO0 and PTO1 pins in the timer out F/F (TOUT F/F) status. The timer out F/F is inverted by a matc...
Page 133 - Figure 6-30. Format of Timer Counter Control Register; No return zero flag; Be sure to clear bits 7 to 0 when setting data to TC2.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 133 User’s Manual U10676EJ3V0UM (3) Timer counter control register (TC2) The timer counter control register (TC2) is an 8-bit register that controls the timer counter (channel 2). Figure 6-30 shows the format of this register. This register controls timer outpu...
Page 134 - -bit programmable interval timer or counter.; to
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 134 User’s Manual U10676EJ3V0UM 6.4.2 Operation in 8-bit timer counter mode In this mode, the timer counter is used as an 8-bit timer counter. In this case, the timer counter operates as an 8-bit programmable interval timer or counter. (1) Register setting In t...
Page 138 - Timer counter output enable flag; Figure 6-33. Setting of Timer Counter Output Enable Flag
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 138 User’s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the 8-bit timer counter mode, set TC2 as shown in Figure 6-32 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ). TC2 is manipulated by an 8- or 4-b...
Page 139 - frequency] selected by the mode register.; Contents of modulo register (n
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 139 User’s Manual U10676EJ3V0UM [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register. T (sec) = = (n+1) (resolution) where, T (sec): Timer set time (seconds) f CP (Hz)...
Page 142 - The timer counter operates as follows.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 142 User’s Manual U10676EJ3V0UM (3) Timer counter operation (8-bit) The timer counter operates as follows. Figure 6-34 shows the configuration when the timer counter operates. <1> The count pulse (CP) is selected by the timer counter mode register (TMn) a...
Page 143 - Figure 6-34. Configuration When Timer Counter Operates; m : Set value of timer counter modulo register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 143 User’s Manual U10676EJ3V0UM Figure 6-34. Configuration When Timer Counter Operates MPX Internal clock Timer counter modulo register (TMODn) Comparator Timer counter count register (Tn) CP TOUT F/F PTOn Coinci-dence Clear INTTn(lRQTn set signal) Figure 6-35....
Page 145 - The timer counter operates as an 8-bit PWM pulse generator.; of Timer Counter Mode Register (Channel 2)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 145 User’s Manual U10676EJ3V0UM 6.4.3 Operation in PWM pulse generator mode (PWM mode) In this mode, the timer counter (channel 2) is used as a PWM pulse generator. The timer counter operates as an 8-bit PWM pulse generator. When the timer counter (channel 2) i...
Page 146 - Figure 6-36. Setting of Timer Counter Mode Register; select bits TM10 and TM11 of the time counter (channel 1) to 0.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 146 User’s Manual U10676EJ3V0UM Figure 6-36. Setting of Timer Counter Mode Register 7 6 5 4 3 2 1 0 TM20 TM21 TM23 TM22 TM24 TM25 TM26 – Address TM2 F90H Symbol TM23 Clears counter and IRQT2 flag when "1" is written. Starts count operationif bit 2 is se...
Page 147 - of Timer Counter Control Register); TC2 is cleared to 00H when the internal reset signal is asserted.; Figure 6-37. Setting of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 147 User’s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the PWM mode, set TC2 as shown in Figure 6-37 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register) . TC2 is manipulated by an 8-, 4-, or bit manipulati...
Page 149 - Figure 6-38. PWM Pulse Generator Operating Configuration; This is the IRQT2 set signal. It is only set when TMOD2 matches T2.; Figure 6-39. PWM Pulse Generator Operating Timing
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 149 User’s Manual U10676EJ3V0UM Figure 6-38. PWM Pulse Generator Operating Configuration Note This is the IRQT2 set signal. It is only set when TMOD2 matches T2. Figure 6-39. PWM Pulse Generator Operating Timing Timer counter (channel 2) operation and carrier c...
Page 152 - Figure 6-40. Setting of Timer Counter Mode Registers
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 152 User’s Manual U10676EJ3V0UM Figure 6-40. Setting of Timer Counter Mode Registers TM20 TM21 TM23 TM22 TM24 TM25 TM26 – TM2 F90H TM23 Clears counter and IRQTn flag when "1" is written. Starts count operationif bit 2 is set to "1". Timer start ...
Page 153 - Figure 6-41. Setting of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 153 User’s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the 16-bit timer counter mode, set TC2 as shown in Figure 6-41 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ). TC2 is manipulated by an 8-, 4-, ...
Page 157 - Figure 6-42. Configuration When Timer Counter Operates
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 157 User’s Manual U10676EJ3V0UM Figure 6-42. Configuration When Timer Counter Operates Otherinternalclock isignored MPX Timer counter modulo register (TMOD1) Comparator Timer counter count register (T1) CP Match Clear T2 overflow MPX CP Comparator Clear TOUT F/...
Page 158 - Set value of timer counter modulo register (TMOD2)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 158 User’s Manual U10676EJ3V0UM Figure 6-43. Timing of Count Operation Remark m: Set value of timer counter module register (TMOD1) n: Set value of timer counter modulo register (TMOD2) Count pulse (CP) Timer counter modulo register (TMOD2) Timer counter count ...
Page 162 - the format of TC2, refer to; Figure 6-30 Format of Timer Counter Control Register; Figure 6-46. Setting of Timer Counter Control Register
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 162 User’s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the CG mode, set the timer counter output enable flag (TOE1) and TC2 as shown in Figure 6-45 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ). TOE...
Page 163 - counter in the carrier generator mode.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 163 User’s Manual U10676EJ3V0UM (2) Carrier generator operation The carrier generator operation is performed as follows. Figure 6-47 shows the configuration of the timer counter in the carrier generator mode. (a) Timer counter (channel 1) operation The timer co...
Page 164 - Figure 6-48 shows the timing of the carrier generator operation.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 164 User’s Manual U10676EJ3V0UM <4> The operations <2> and <3> are repeated. <5> The no return zero data is reloaded from NRZB to NRZ when timer counter channel 1 generates an interrupt. <6> A carrier clock or high level is output ...
Page 165 - Figure 6-47. Configuration in Carrier Generator Mode
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 165 User’s Manual U10676EJ3V0UM Figure 6-47. Configuration in Carrier Generator Mode Otherinternalclock isignored MPX Timer countermodulo register (TMOD1) Comparator Timer countercount register (T1) CP Clear TOUT F/F PTO1 PTO2 Carrier clock NRZB NRZ High-level ...
Page 166 - Figure 6-48. Carrier Generator Operation Timing
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 166 User’s Manual U10676EJ3V0UM Figure 6-48. Carrier Generator Operation Timing <1> Timer (channel 2) operation and carrier clock (Modulo register H (TMOD2H) = i, Modulo register (TMOD2) = k) Count pulse (CP) Timer counter count register (T2) Carrier cloc...
Page 167 - from the pulse after the carrier clock.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 167 User’s Manual U10676EJ3V0UM Remark If a timer (channel 1) interrupt is generated when the PTO2 pin is low and the carrier clock is high (NRZ = 0, carrier clock = high level), the carrier is output to the PTO2 pin from the pulse after the carrier clock. If a...
Page 170 - and timer start command.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 170 User’s Manual U10676EJ3V0UM <3> To output a custom code with a 0.56 ms period to output a carrier clock when data is “1”, a 1.69 ms to output a low level, a 0.56 ms to output a carrier clock when data is “0”, and a 0.56 ms period to output a low level...
Page 173 - resolution, deviates by up
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 173 User’s Manual U10676EJ3V0UM 6.4.6 Notes on using timer counter (1) Error when timer starts After the timer has been started (bit 3 of TMn has been set to “1”), the time required for generation of the match signal, which is calculated by the expression (cont...
Page 176 - (4) Operation after changing modulo register; changing TMODn and TMOD2H.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 176 User’s Manual U10676EJ3V0UM (4) Operation after changing modulo register The contents of the timer counter modulo register (TMODn) and high-level period setting timer counter modulo register (TMOD2H) are changed as soon as an 8-bit data memory manipulation ...
Page 177 - an error that may occur when the timer is started.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 177 User’s Manual U10676EJ3V0UM (5) Note on application of carrier generator (on starting) When the carrier clock is generated, after the timer has been started (by setting bit 3 of TM2 to “1”), the high- level period of the initial carrier clock may deviate by...
Page 178 - hold constant the high-level period of the carrier.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 178 User’s Manual U10676EJ3V0UM (6) Notes on application of carrier generator (reload) To output a carrier to the PTO2 pin, the time required for the initial carrier to be generated deviates by up to one carrier clock after reloading (the contents of the no ret...
Page 179 - carrier may not be output to the PTO2 pin as shown below.; the carrier output to the PTO2 pin may be extended as shown below.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 179 User’s Manual U10676EJ3V0UM (7) Notes on application of carrier generator (restarting) If forced reloading is performed by directly rewriting the contents of the no return zero flag (NRZ) and then the timer is restarted (by setting bit 3 of TM2 to “1”) when...
Page 180 - Configuration and operation of programmable threshold port
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 180 User’s Manual U10676EJ3V0UM 6.5 Programmable Threshold Port (Analog Input Port) The µ PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performe...
Page 181 - Figure 6-49. Block Diagram of Programmable Threshold Port
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 181 User’s Manual U10676EJ3V0UM Figure 6-49. Block Diagram of Programmable Threshold Port PTH00 PTH01 AV REF 12 R R R 12 R MPX V REF PTHM7 PTHM PTHM6 PTHM5 PTHM4 PTHM3 PTHM2 PTHM1 PTHM0 8 Operate/stop Standby mode signal + – + – PTH0 Programmable threshold port...
Page 182 - memory manipulation instruction.; Bit 4 and 5 of PTHM must be set to “0”.; Comparator operation mode specification; Values in parentheses are applicable when f; Threshold voltage selection
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 182 User’s Manual U10676EJ3V0UM 0.5 16 15.5 16 6.5.2 Programmable threshold port mode (PTHM) register PTHM is an 8-bit register that controls the programmable threshold port operation, and it is set by an 8-bit memory manipulation instruction. The threshold vol...
Page 183 - Programmable threshold port application; Buffer
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 183 User’s Manual U10676EJ3V0UM 6.5.3 Programmable threshold port application (1) An analog input voltage input to the PTH00 pin is A/D converted with 4-bit resolution. Figure 6-51. Application Example of Programmable Threshold Port PTH00 input voltage Referenc...
Page 184 - long bit length in bit units.; Figure 6-52. Format of Bit Sequential Buffer; specification of MBE and MBS.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 184 User’s Manual U10676EJ3V0UM 6.6 Bit Sequential Buffer ... 16 Bits The bit sequential buffer (BSB) is a special data memory used for bit manipulation. It can manipulate bits by sequentially changing the address and bit specification. Therefore, this buffer i...
Page 186 - CHAPTER 7 INTERRUPT AND TEST FUNCTIONS; Configuration of Interrupt Controller
186 User’s Manual U10676EJ3V0UM CHAPTER 7 INTERRUPT AND TEST FUNCTIONS The µ PD754244 has six vectored interrupt sources and one test input that can be used for various applications. The interrupt controller of the µ PD754244 has unique features and can service interrupts at extremely high speed. (1...
Page 187 - CHAPTER 7 INTERRUPT AND TEST FUNCTIONS; Figure 7-1. Block Diagram of Interrupt Controller
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 187 User’ s Man ual U10676EJ3V0UM Figure 7-1. Block Diagram of Interrupt Controller Notes 1. Noise eliminator (Standby release is disable when noise eliminator is selected.) 2. Does not have the INT2 pin. The interrupt request flag (IRQ2) is set at the KRn pin ...
Page 188 - Types of Interrupt Sources and Vector Table
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 188 User’s Manual U10676EJ3V0UM 7.2 Types of Interrupt Sources and Vector Table The µ PD754244 has the following six interrupt sources and nesting of interrupts can be controlled by software. Table 7-1. Types of Interrupt Sources Interrupt Source Internal/Exter...
Page 189 - Setting of vector table of INTBT; are stored in the vector table address at address 2n.; Setting of vector tables of INTBT and INTT0
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 189 User’s Manual U10676EJ3V0UM Figure 7-2. Interrupt Vector Table MBE MBE MBE MBE MBE Address 0002H 0004H 0006H 0008H 000AH 000CH 000EH RBE RBE RBE RBE RBE INTBT start address (higher 4 bits) INTBT start address (lower 8 bits) INT0 start address (higher 4 bits...
Page 190 - Hardware Controlling Interrupt Function; (1) Interrupt request flag and interrupt enable flag
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 190 User’s Manual U10676EJ3V0UM 7.3 Hardware Controlling Interrupt Function (1) Interrupt request flag and interrupt enable flag The µ PD754244 has the following six interrupt request flags (IRQ ××× ) corresponding to the respective interrupt sources. INT0 inte...
Page 191 - Table 7-2. Signals Setting Interrupt Request Flags
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 191 User’s Manual U10676EJ3V0UM Table 7-2. Signals Setting Interrupt Request Flags Interrupt Request Flag Signal Setting Interrupt Request Flag Interrupt Enable Flag Set by reference time interval signal from basic interval timer watchdog timer Set by detection...
Page 192 - Figure 7-3. Interrupt Priority Select Register; Selection of higher-priority interrupts; not give high priority to any interrupt.)
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 192 User’s Manual U10676EJ3V0UM Figure 7-3. Interrupt Priority Select Register IPS3 IPS2 IPS1 IPS0 3 2 1 0 IPS Symbol FB2H Address 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 No interrupts are handled as higher-priority interrupts. VRQ1 (INTBT) VRQ2 (INT0) ...
Page 194 - Even if f
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 194 User’s Manual U10676EJ3V0UM Figure 7-4. Configuration of INT0 Internal bus 4 IM0 Noise eliminator INT0/P61 Selector Selector Φ f X /64 IM03 Edge detector INT0 (IRQ0 set signal) IM00, IM01 IM02 Specifies edge to be detected. Selects sampling clock. Input buf...
Page 195 - This value differs depending on the system clock frequency (f
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 195 User’s Manual U10676EJ3V0UM Figure 7-6. Format of INT0 Edge Detection Mode Register (IM0) 3 2 1 0 IM00 IM01 IM02 IM03 Address IM0 FB4H Symbol IM01 Specifies edge to be detected IM00 0 Rising edge 0 0 Falling edge 1 1 Both rising and falling edges 0 1 Ignore...
Page 196 - Table 7-3. IST1 and IST0 and Interrupt Servicing Status
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 196 User’s Manual U10676EJ3V0UM (4) Interrupt status flag The interrupt status flags (IST0 and IST1) indicate the status of the processing currently being executed by the CPU and are included in PSW. The interrupt priority controller controls nesting of interru...
Page 197 - Interrupt Sequence; Figure 7-7. Interrupt Servicing Sequence; IST1 and 0: Interrupt status flags (bits 3 and 2 of PSW Refer to
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 197 User’s Manual U10676EJ3V0UM 7.4 Interrupt Sequence When an interrupt occurs, it is processed according to the procedure illustrated below. Figure 7-7. Interrupt Servicing Sequence Interrupt (INT ××× ) occurs Sets IRQ ××× IE ××× set? Corresponding VRQn occur...
Page 198 - Nesting Control of Interrupts; (1) Nesting with interrupt having high priority specified
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 198 User’s Manual U10676EJ3V0UM 7.5 Nesting Control of Interrupts The µ PD754244 can nest interrupts by the following two methods. (1) Nesting with interrupt having high priority specified This method is the standard nesting method of the µ PD754244. One interr...
Page 199 - (2) Nesting by changing interrupt status flags
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 199 User’s Manual U10676EJ3V0UM (2) Nesting by changing interrupt status flags Nesting can be implemented if the interrupt status flags are changed by program. In other words, nesting is enabled when IST1 and IST0 are cleared to “0, 0” by an interrupt servicing...
Page 200 - Servicing of Interrupts Sharing Vector Address; Table 7-4. Identifying Interrupt Sharing Vector Address
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 200 User’s Manual U10676EJ3V0UM 7.6 Servicing of Interrupts Sharing Vector Address Because interrupt sources INTT1 and INTT2 share vector tables, you should select one or both of the interrupt sources in the following way. (1) To use one interrupt Of the two in...
Page 201 - Examples
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 201 User’s Manual U10676EJ3V0UM Examples 1. To use both INTT1 and INTT2 as having higher priority, and give priority to INTT2 DI SKTCLR IRQT2 ; IRQT2=1? BR VSUBBT EI RETI : VSUBBT: CLR1 IRQT1 EI RETI 2. To use both INTT1 and INTT2 as having lower priority, and ...
Page 202 - Machine Cycles Until Interrupt Servicing; routine is executed is as follows.; Sets IRQxxx; Remarks; manipulated when an interrupt is acknowledged.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 202 User’s Manual U10676EJ3V0UM 7.7 Machine Cycles Until Interrupt Servicing The number of machine cycles required from when an interrupt request flag (IRQxxx) has been set until the interrupt routine is executed is as follows. (1) If IRQxxx is set while interr...
Page 204 - Effective Usage of Interrupts; Use the interrupt function effectively as follows.; Application of Interrupt
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 204 User’s Manual U10676EJ3V0UM 7.8 Effective Usage of Interrupts Use the interrupt function effectively as follows. (1) Use different register banks for the normal routine and interrupt routine. The normal routine uses register banks 2 and 3 with RBE = 1 and R...
Page 205 - <2> An interrupt enable flag is set by the EI IE
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 205 User’s Manual U10676EJ3V0UM (1) Enabling or disabling interrupt Reset . . . <1> EI IE0EI IET1 <2> EI . . . . . . <3> DI IE0 . . . . . . <4> DI . . . . . . . . . . . . . . . . <5> Disablesinterrupts Enables INT0 and INTT1 Enable...
Page 206 - to 0 and interrupts are enabled.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 206 User’s Manual U10676EJ3V0UM (2) Example of using INTBT and INT0 (falling edge active): not nested (all interrupts have higher priority) SEL <1> Reset INT0 <4> RB2 MOV MOV CLR1 <2> A, #1 IM0, A IRQ0 EI EI EI EI . . . . . . . . . . . . . . ....
Page 207 - interrupts are disabled.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 207 User’s Manual U10676EJ3V0UM (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTT2 have lower priority) <1> Reset INTT0 <2> SEL EI EI EI MOV MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 210 - interrupt with the lower priority is held pending.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 210 User’s Manual U10676EJ3V0UM (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) - Reset EI IEBT EI IET0 EI IET2 MOV A, #9 MOV IPS, A . . . . . . . . . . . . . . . . ...
Page 212 - Hardware controlling test function
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 212 User’s Manual U10676EJ3V0UM 7.10 Test Function 7.10.1 Types of test sources The µ PD754244 has a test source, INT2. INT2 is an edge-detection testable input. Table 7-5. Types of Test Sources Test Source Internal/External INT2 (detects falling edge of input ...
Page 213 - Figure 7-10. Block Diagram of KR4 to KR7
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 213 User’s Manual U10676EJ3V0UM Figure 7-10. Block Diagram of KR4 to KR7 KR7/P73 KR6/P72 KR5/P71 KR4/P70 Nothing is assigned(in reset mode) Key return reset circuit Falling edge detector IM2 INT2 (IRQ2 setting signal) Input buffer 4 Internal bus Selector
Page 214 - If a low level is input to even one of the KR
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 214 User’s Manual U10676EJ3V0UM Figure 7-11. Format of INT2 Edge Detection Mode Register (IM2) 3 2 1 0 IM20 IM21 0 0 Address IM2 FB6H Symbol IM21 INT2 test source IM20 0 Assigned nothing 0 0 1 Other Test input pin – KR4-KR7 Inputs falling edge of any of KR4/P70...
Page 215 - CHAPTER 8 STANDBY FUNCTION; Cautions
215 User’s Manual U10676EJ3V0UM CHAPTER 8 STANDBY FUNCTION The µ PD754244 possesses a standby function that reduces the power consumption of the system. This standby function can be implemented in the following two modes. • STOP mode • HALT mode The functions of the STOP and HALT modes are as follow...
Page 216 - CHAPTER 8 STANDBY FUNCTION; Settings and Operating Statuses of Standby Mode; Table 8-1. Operating Statuses in Standby Mode
CHAPTER 8 STANDBY FUNCTION 216 User’s Manual U10676EJ3V0UM 8.1 Settings and Operating Statuses of Standby Mode Table 8-1. Operating Statuses in Standby Mode STOP Mode HALT Mode Instruction to be set STOP instruction HALT instruction Operating status Clock generator Operation stopped Only CPU clock Φ...
Page 217 - and HALT instructions respectively set bits 3 and 2 of PCC).
CHAPTER 8 STANDBY FUNCTION 217 User’s Manual U10676EJ3V0UM The STOP mode is set by the STOP instruction, and the HALT mode is set by the HALT instruction (the STOP and HALT instructions respectively set bits 3 and 2 of PCC). Be sure to write a NOP instruction after the STOP and HALT instructions. Wh...
Page 218 - Releasing Standby Mode; Figure 8-1 illustrates how each mode is released.; (a) Releasing STOP mode by RESET signal, or by key return reset; PD754244: The following two times can be selected by mask option.
CHAPTER 8 STANDBY FUNCTION 218 User’s Manual U10676EJ3V0UM 8.2 Releasing Standby Mode Both the STOP and HALT modes can be released when an interrupt request signal occurs that is enabled by the corresponding interrupt enable flag, or when the RESET signal is asserted. Furthermore, STOP mode can be r...
Page 221 - Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input
CHAPTER 8 STANDBY FUNCTION 221 User’s Manual U10676EJ3V0UM Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input IE ×××← 0 STOP NOP Key return resetor RESET input The differences between release by a key return reset and release by RESET input are as follows. RESET Input Key Return Reset ...
Page 222 - Operation After Release of Standby Mode; has been released. The interrupt request flag is retained.; Application of Standby Mode; Use the standby mode according to the following procedure.; on whether interrupt servicing is performed or not).
CHAPTER 8 STANDBY FUNCTION 222 User’s Manual U10676EJ3V0UM 8.3 Operation After Release of Standby Mode (1) When the standby mode has been released by the RESET signal, the normal reset operation is performed. (2) When the standby mode has been released by an interrupt, whether or not a vectored inte...
Page 223 - ; INT0 pin is checked twice to prevent chattering.
CHAPTER 8 STANDBY FUNCTION 223 User’s Manual U10676EJ3V0UM (1) Application example of STOP mode (when using the µ PD754244 at f X = 6.0 MHz) <When using the STOP mode under the following conditions> • The STOP mode is set at the falling edge of INT0 and released at the rising edge. • All the I...
Page 225 - • INT0 and INTBT are assigned a lower priority.
CHAPTER 8 STANDBY FUNCTION 225 User’s Manual U10676EJ3V0UM (2) Application example of HALT mode (when using the µ PD754244 at f X = 6.0 MHz) <To perform intermittent operation under the following conditions> • The standby mode is set at the falling edge of INT0 and released at the rising edge....
Page 227 - Figure 9-1. Configuration of Reset Circuit; the timing of the reset operation.
227 User’s Manual U10676EJ3V0UM CHAPTER 9 RESET FUNCTION 9.1 Configuration and Operation of Reset Function Three types of reset signals are used: the external reset signal (RESET), a reset signal from the basic interval timer/watchdog timer, and a key return reset. When any one of these reset signal...
Page 228 - CHAPTER 9 RESET FUNCTION; Figure 9-2. Reset Operation by RESET Signal
CHAPTER 9 RESET FUNCTION 228 User’s Manual U10676EJ3V0UM Figure 9-2. Reset Operation by RESET Signal RESET signal HALT mode Operation mode or standby mode Internal reset operation Operation mode Wait Note Note µ PD754244: The following two times can be selected by the mask option. 2 17 /f X (21.8 ms...
Page 231 - WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively.; Table 9-2. WDF and KRF Contents Corresponding to Each Signal
CHAPTER 9 RESET FUNCTION 231 User’s Manual U10676EJ3V0UM 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively. The contents of WDF and KRF are undefined initially, but they are initialized to “0” by external RESET signal generation. WDF is...
Page 232 - Figure 9-4. KRF Operation in Generating Each Signal
CHAPTER 9 RESET FUNCTION 232 User’s Manual U10676EJ3V0UM Figure 9-4. KRF Operation in Generating Each Signal External RESET KRF Operation mode Operation mode HALT mode Operation mode Internal reset operation STOP mode Internal reset operation Internal reset operation HALT mode Operation mode STOP mo...
Page 233 - CHAPTER 10 MASK OPTIONS; Pin Mask Options; Releasing Standby Mode
233 User’s Manual U10676EJ3V0UM CHAPTER 10 MASK OPTIONS The µ PD754144 and 754244 have the following mask options. Table 10-1. Selection of Mask Options Item µ PD754144 µ PD754244 P70/KR4 to P73/KR7 On-chip pull-up resistors specifiable in 1-bit units by mask option RESET pin On-chip pull-up resisto...
Page 234 - CHAPTER 11 INSTRUCTION SET; The instruction set of the; (1) Bit manipulation instructions for various applications; Unique Instructions; This section describes the instructions unique to the
234 User’s Manual U10676EJ3V0UM CHAPTER 11 INSTRUCTION SET The instruction set of the µ PD754244 is based on the instruction set of the 75X Series and therefore maintains compatibility with the 75X Series, but with the following improved features. (1) Bit manipulation instructions for various applic...
Page 235 - CHAPTER 11 INSTRUCTION SET
CHAPTER 11 INSTRUCTION SET 235 User’s Manual U10676EJ3V0UM 11.1.2 Bit manipulation instruction The µ PD754244 has reinforced bit test, bit transfer, and bit Boolean (AND, OR, and XOR) instructions, in addition to the ordinary bit manipulation (set and clear) instructions. The bit to be manipulated i...
Page 236 - Base number adjustment instruction; or subtraction of 4-bit data into a number with any base.; (1) Base adjustment of result of addition; Occurrence of an overflow is indicated by the carry flag.; To add accumulator and memory in decimal; (2) Base adjustment of result of subtraction; of subtraction is adjusted to a number with a base of m.
CHAPTER 11 INSTRUCTION SET 236 User’s Manual U10676EJ3V0UM 11.1.4 Base number adjustment instruction Some applications require that the result of addition or subtraction of 4-bit data (which is carried out in binary) be converted into a decimal number or into a number with a base of 6, such as time....
Page 237 - Instruction Set and Operation; (1) Operand representation and description; and
CHAPTER 11 INSTRUCTION SET 237 User’s Manual U10676EJ3V0UM 11.1.5 Skip instruction and number of machine cycles required for skipping The instruction set of the µ PD754244 configures a program where instructions may be or may not be skipped if a given condition is satisfied. If a skip condition is s...
Page 239 - (2) Conventions for explanation of operation
CHAPTER 11 INSTRUCTION SET 239 User’s Manual U10676EJ3V0UM (2) Conventions for explanation of operation A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA); 8-bit accumulator BC: Register pair (BC) ...
Page 241 - The value of S varies as follows.; One machine cycle is equal to one cycle of CPU clock; Figure 6-15 Processor Clock Control Register Format
CHAPTER 11 INSTRUCTION SET 241 User’s Manual U10676EJ3V0UM (4) Explanation of machine cycle field S indicates the number of machine cycles required for an instruction with skip to execute the skip operation. The value of S varies as follows. • When skip is executed .....................................
Page 243 - Set 0 to the B register.
CHAPTER 11 INSTRUCTION SET 243 User’s Manual U10676EJ3V0UM Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area MOVT XA, @PCDE 1 3 XA ← (PC 11-8 + DE) ROM XA, @PCXA 1 3 XA ← (PC 11-8 + XA) ROM XA, @BCDE 1 3 XA ← (BCDE) ROM Note *6 XA, @BCXA 1 3 XA ← (BCXA) ROM N...
Page 245 - PCDE; BRA; Set 0 to the B register
CHAPTER 11 INSTRUCTION SET 245 User’s Manual U10676EJ3V0UM Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area AND1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY (pmem 7-2 + L 3-2 .bit(L 1-0 )) *5 CY, @H + mem.bit 2 2 CY ← CY (H + mem 3-0 .bit)...
Page 248 - Opcode of Each Instruction
CHAPTER 11 INSTRUCTION SET 248 User’s Manual U10676EJ3V0UM 11.3 Opcode of Each Instruction (1) Description of symbol of opcode R 2 R 1 R 0 reg 0 0 0 A 0 0 1 X 0 1 0 L 0 1 1 H 1 0 0 E 1 0 1 D 1 1 0 C 1 1 1 B reg reg1 P 2 P 1 P 0 reg-pair 0 0 0 XA 0 0 1 XA' 0 1 0 HL 0 1 1 HL' 1 0 0 DE 1 0 1 DE' 1 1 0 ...
Page 249 - (2) Opcode for bit manipulation addressing; *1 in the operand field indicates the following three types.
CHAPTER 11 INSTRUCTION SET 249 User’s Manual U10676EJ3V0UM (2) Opcode for bit manipulation addressing *1 in the operand field indicates the following three types. • fmem.bit • pmem.@L • @H+mem.bit The second byte *2 of the opcode corresponding to the above addressing is as follows. *1 2nd Byte of Op...
Page 254 - Instruction Function and Application; How to read; : This instruction can be used only in the MkI mode of the; II
CHAPTER 11 INSTRUCTION SET 254 User’s Manual U10676EJ3V0UM 11.4 Instruction Function and Application This section describes the functions and applications of the respective instructions. The instructions that can be used and the functions of the instructions differ between the MkI and MkII modes of ...
Page 255 - Application example
CHAPTER 11 INSTRUCTION SET 255 User’s Manual U10676EJ3V0UM 11.4.1 Transfer instructions MOV A, #n4 Function: A ← n4 n4 = I 3-0 : 0-FH Transfers 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a string effect (group A), and if MOV A, #n4 or MOV XA, #n8 follows this...
Page 256 - the next instruction is skipped.
CHAPTER 11 INSTRUCTION SET 256 User’s Manual U10676EJ3V0UM MOV A, @HL Function: A ← (HL) Transfers the contents of the data memory content addressed by register pair HL is transferred to the A register. MOV A, @HL+ Function: A ← (HL), L ← L+1 skip if L = 0H Transfers the contents of the data memory ...
Page 260 - The address that can be specified by mem is an even address.
CHAPTER 11 INSTRUCTION SET 260 User’s Manual U10676EJ3V0UM XCH XA, @HL Function: A ↔ (HL), X ↔ (HL+1) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL, and the contents of the X register with the contents of the next address. If the contents...
Page 261 - XA
CHAPTER 11 INSTRUCTION SET 261 User’s Manual U10676EJ3V0UM 11.4.2 Table reference instructions MOV XA, @PCDE Function: XA ← ROM (PC 11-8 +DE) Transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (PC 7-0 ) of the program counter (PC) are replaced with the...
Page 266 - Base number adjustment instruction
CHAPTER 11 INSTRUCTION SET 266 User’s Manual U10676EJ3V0UM 11.4.4 Operation instructions ADDS A, #n4 Function: A ← A+n4; Skip if carry. n4 = l 3-0 : 0 to FH Adds 4-bit immediate data n4 to the contents of the A register. If a carry occurs as a result, the next instruction is skipped. The carry flag ...
Page 267 - can be used in combination for base number adjustment (refer to; The carry flag is not affected.
CHAPTER 11 INSTRUCTION SET 267 User’s Manual U10676EJ3V0UM ADDC A, @HL Function: A, CY ← A+ (HL) +CY Adds the contents of the data memory addressed by register pair HL to the contents of the A register, including the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry...
Page 272 - Accumulator manipulation instructions; RORC A; NOT A
CHAPTER 11 INSTRUCTION SET 272 User’s Manual U10676EJ3V0UM 11.4.5 Accumulator manipulation instructions RORC A Function: CY ← A 0 , A n-1 ← A n , A 3 ← CY (n = 1-3) Rotates the contents of the A register (4-bit accumulator) 1 bit to the left with the carry flag. 0 CY 0 3 1 2 0 1 1 0 A Before executi...
Page 273 - INCS reg
CHAPTER 11 INSTRUCTION SET 273 User’s Manual U10676EJ3V0UM 11.4.6 Increment/decrement instructions INCS reg Function: reg ← reg+1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L, D, E, B, or C). If reg = 0 as a result, the next instruction is skipped. INCS rp1 Function: rp1 ← rp...
Page 275 - Carry flag manipulation instructions; SET1 CY
CHAPTER 11 INSTRUCTION SET 275 User’s Manual U10676EJ3V0UM 11.4.8 Carry flag manipulation instructions SET1 CY Function: CY ← 1 Sets the carry flag. CLR1 CY Function: CY ← 0 Clears the carry flag. SKT CY Function: Skip if CY = 1 Skips the next instruction if the carry flag is 1. NOT1 CY Function: CY...
Page 276 - Memory bit manipulation instructions
CHAPTER 11 INSTRUCTION SET 276 User’s Manual U10676EJ3V0UM 11.4.9 Memory bit manipulation instructions SET1 mem.bit Function: (mem.bit) ← 1 mem = D 7-0 : 00H to FFH, bit = B 1-0 : 0-3 Sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem. SET1 fmem.b...
Page 279 - BR addr
CHAPTER 11 INSTRUCTION SET 279 User’s Manual U10676EJ3V0UM 11.4.10 Branch instructions BR addr Function: PC 11-0 ← addr addr = 0000H to 0FFFH Branches to an address specified by immediate data addr. This instruction is an assembler directive and is replaced by the assembler at assembly time with the...
Page 281 - BR PCDE; BR PCXA
CHAPTER 11 INSTRUCTION SET 281 User’s Manual U10676EJ3V0UM BR PCDE Function: PC 11-0 ← PC 11-8 + DE PC 7-4 ← D, PC 3-0 ← E Branches to an address specified by the lower 8 bits of the program counter (PC 7-0 ) replaced with the contents of register pair DE. The higher bits of the program counter are ...
Page 282 - BR BCDE; BR BCXA; TBR addr; Assembler Package Language User’s Manual
CHAPTER 11 INSTRUCTION SET 282 User’s Manual U10676EJ3V0UM BR BCDE Function: PC 11-0 ← BCDE Example To branch to an address specified by the contents of the program counter replaced by the contents of registers B, C, D, and E However, the PC of the µ PD754244 is 12 bits. The contents of PC are repla...
Page 285 - RET; RETS; RETI
CHAPTER 11 INSTRUCTION SET 285 User’s Manual U10676EJ3V0UM RET Function: [MkI mode] PC 11-8 ← (SP), MBE, RBE, 0, 0 ← (SP+1) PC 3-0 ← (SP+2) PC 7-4 ← (SP+3), SP ← SP+4 [MkII mode] PC 11-8 ← (SP), 0, 0, 0, 0 ← (SP+1) PC 3-0 ← (SP+2), PC 7-4 ← (SP+3) × , × , MBE, RBE ← (SP+4), SP ← SP+6 Restores the co...
Page 286 - PUSH rp; rp; PUSH BS; Function; or BC), and then decrements the contents of the stack pointer.; POP BS; RBS
CHAPTER 11 INSTRUCTION SET 286 User’s Manual U10676EJ3V0UM PUSH rp Function: (SP–1) ← rp H , (SP–2) ← rp L , SP ← SP–2 Saves the contents of register pair rp (XA, HL, DE, or BC) to the data memory (stack) addressed by the stack pointer (SP), and then decrements the contents of the SP. The higher 4 b...
Page 287 - EI
CHAPTER 11 INSTRUCTION SET 287 User’s Manual U10676EJ3V0UM 11.4.12 Interrupt control instructions EI Function: IME (IPS.3) ← 1 Sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “1” to enable interrupts. Acknowledging an interrupt is controlled by an interrupt e...
Page 288 - to the register in the input mode.
CHAPTER 11 INSTRUCTION SET 288 User’s Manual U10676EJ3V0UM 11.4.13 Input/output instructions IN A, PORTn Function: A ← PORTn n = N 3-0 : 3, 6, 7, 8 Transfers the contents of a port specified by PORTn (n = 3, 6, 7, 8) to the A register. Caution When this instruction is executed, it is necessary that ...
Page 289 - HALT; Make sure that a NOP instruction follows the HALT instruction.; STOP; Make sure that a NOP instruction follows the STOP instruction.; NOP; Executes nothing but consumes 1 machine cycle.
CHAPTER 11 INSTRUCTION SET 289 User’s Manual U10676EJ3V0UM 11.4.14 CPU control instruction HALT Function: PCC.2 ← 1 Sets the HALT mode (this instruction sets the bit 2 of the processor clock control register). Caution Make sure that a NOP instruction follows the HALT instruction. STOP Function: PCC....
Page 290 - SEL RBn; When table defined by TBR instruction is referenced; When table defined by TCALL instruction is referenced
CHAPTER 11 INSTRUCTION SET 290 User’s Manual U10676EJ3V0UM 11.4.15 Special instructions SEL RBn Function: RBS ← n n = N 1-0 : 0-3 Sets 2-bit immediate data n to the register bank select register (RBS). SEL MBn Function: MBS ← n n = N 3-0 : 0, 4, 15 Transfers 4-bit immediate data n to the memory bank...
Page 293 - APPENDIX A DEVELOPMENT TOOLS; combination with a device file dedicated to the model being used.; Language Processor; OS of IBM
293 User’s Manual U10676EJ3V0UM APPENDIX A DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µ PD754244. With the 75XL Series, a relocatable assembler that can be used in common with any model in the series is used in combination with a devic...
Page 294 - APPENDIX A DEVELOPMENT TOOLS; Debugging Tools; This is a maintenance part.
APPENDIX A DEVELOPMENT TOOLS 294 User’s Manual U10676EJ3V0UM EV-9500GS-20 EV-9501GS-20 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are available as the debugging tools for the µ PD754244. The following table shows the system configuration of the in-circuit emulators. Hardware Or...
Page 295 - OS of IBM PC
APPENDIX A DEVELOPMENT TOOLS 295 User’s Manual U10676EJ3V0UM OS of IBM PC The following OSs are supported as the OS for IBM PCs. OS Version PC DOS TM Ver.5.02 to Ver.6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver.5.0 to Ver.6.22 5.0/V Note to 6.2/V Note IBM DOS TM J5.02/V Note Note Only the English mode ...
Page 296 - Development Tool Configuration
APPENDIX A DEVELOPMENT TOOLS 296 User’ s Man ual U10676EJ3V0UM Development Tool Configuration In-circuit emulator IE-75000-R or IE-75001-R Emulation board IE-75300-R-EM Note 1 IE control program Host machine PC-9800 series lBM PC/AT [Symbolic debugging possible] Relocatable assembler + Device file R...
Page 297 - APPENDIX B ORDERING MASK ROM
297 User’s Manual U10676EJ3V0UM APPENDIX B ORDERING MASK ROM After your program has been developed, you can place an order for mask ROM using the following procedure. <1> Reservation for mask ROM ordering Inform NEC Electronics of when you intend to place an order for the mask ROM. (NEC’s resp...
Page 298 - APPENDIX C INSTRUCTION INDEX
298 User’s Manual U10676EJ3V0UM APPENDIX C INSTRUCTION INDEX C.1 Instruction Index (By Function) [Table reference instruction] MOVT XA, @PCDE ... 243, 261 MOVT XA, @PCXA ... 243, 263 MOVT XA, @BCDE ... 243, 263 MOVT XA, @BCXA ... 243, 264 [Bit transfer instruction] MOV1 CY, fmem.bit ... 243, 265 MOV...
Page 299 - APPENDIX C INSTRUCTION INDEX
APPENDIX C INSTRUCTION INDEX 299 User’s Manual U10676EJ3V0UM AND A, @HL ... 243, 269 AND XA, rp' ... 243, 269 AND rp'1, XA ... 243, 269 OR A, #n4 ... 243, 270 OR A, @HL ... 243, 270 OR XA, rp' ... 243, 270 OR rp'1, XA ... 243, 270 XOR A, #n4 ... 243, 270 XOR A, @HL ... 243, 271 XOR XA, rp' ... 243, ...
Page 304 - APPENDIX D HARDWARE INDEX
304 User’s Manual U10676EJ3V0UM APPENDIX D HARDWARE INDEX [B] BS ... 78 BSB0 to BSB3 ... 184 BT ... 114 BTM ... 115 [C] CY ... 74 [E] ERE ... 81 EWC ... 81 EWE ... 81 EWST ... 81 EWTC4 to EWTC6 ... 81 [I] IE0 ... 190 IE2 ... 212 IEBT ... 190 IEEE ... 82, 190 IET0 ... 190 IET1 ... 190 IET2 ... 190 IM...
Page 305 - APPENDIX D HARDWARE INDEX
APPENDIX D HARDWARE INDEX 305 User’s Manual U10676EJ3V0UM [S] SBS ... 61, 70 SK0 to SK2 ... 75 SP ... 70 [T] T0, T1 ... 54 T2 ... 53 TC2 ... 133, 138 TM0 ... 127 TM1 ... 128 TM2 ... 130 TMOD0, TMOD1 ... 54 TMOD2 ... 53 TMOD2H ... 52 TOE0, TOE1 ... 132 TOE2 ... 133 [W] WDF ... 231 WDTM ... 117
Page 306 - APPENDIX E REVISION HISTORY
306 User’s Manual U10676EJ3V0UM APPENDIX E REVISION HISTORY The revision history is shown below. “Location” indicates the corresponding chapters in the preceding edition. Edition Description Location 2nd edition Change of representative model from µ PD754144 to µ PD754244 Throughout Change of EEPROM...
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