NEC PD754244 - Manual

NEC PD754244

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Table of Contents:

  • Page 3 – EEPROM is a trademark of NEC Electronics Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
  • Page 4 – s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .
  • Page 5 – Regional Information; Device availability; NEC Electronics Hong Kong Ltd.
  • Page 6 – Major Revisions in This Edition; and INTT2 have lower priority); The mark
  • Page 7 – INTRODUCTION
  • Page 8 – Related Documents; However, preliminary versions are not marked as such.; Documents related to devices
  • Page 9 – AV
  • Page 16 – LIST OF TABLES; Title
  • Page 17 – CHAPTER 1 GENERAL; APPLICATIONS
  • Page 18 – CHAPTER 1 GENERAL; Functional Outline
  • Page 19 – Ordering Information; Part Number; Remark; indicates ROM code suffix.; Differences Between Series Products
  • Page 21 – Pin configuration of; IC: Internally Connected (Directly connect to V
  • Page 23 – Pin Name
  • Page 24 – Circled characters indicate Schmitt-triggered input.
  • Page 25 – CHAPTER 2 PIN FUNCTIONS; Note; Circled characters indicate Schmitt triggered input.
  • Page 26 – Description of Pin Functions; Port 6: Programmable threshold port reference voltage input (AV; Generation of the RESET signal sets the input mode.
  • Page 27 – (c) Active at both rising and falling edges
  • Page 28 – No external clock can be input.; RC oscillation; An external clock can also be input to these pins.
  • Page 30 – The following diagrams show the I/O circuits of the pins of the
  • Page 31 – Processing of Unused Pins; Table 2-3. Recommended Connection of Unused Pins
  • Page 33 – CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
  • Page 34 – Example
  • Page 39 – Figure 3-3. Updating Address of Static RAM
  • Page 45 – Bank Configuration of General-Purpose Registers; Table 3-2. Register Bank Selected by RBE and RBS
  • Page 46 – Figure 3-4. Example of Using Register Banks
  • Page 56 – These are not registered as reserved words.
  • Page 60 – Difference between MkI and MkII modes; The CPU of the; Table 4-1. Differences Between MkI and MkII Modes
  • Page 61 – CHAPTER 4 INTERNAL CPU FUNCTION; Figure 4-1. Format of Stack Bank Select Register; Specifies stack area
  • Page 62 – Figure 4-2. Configuration of Program Counter; each time that instruction has been executed.
  • Page 63 – bits; program memory addresses.; used to decrease the number of program steps (refer to
  • Page 64 – Can be used in the MkII mode only.; by means of a BR PCDE or BR PCXA instruction.
  • Page 65 – bits; General-purpose register area
  • Page 66 – the bank are specified by 8-bit immediate data or a register pair.; Bank Configuration of Data Memory and
  • Page 69 – Configuration of General-Purpose Registers; whether the registers in this area are used or not.; Figure 4-6. Configuration of Register Pair
  • Page 71 – Example of SP initialization
  • Page 73 – The contents of PSW other than MBE and RBE are not saved or restored.
  • Page 74 – Figure 4-13. Configuration of Program Status Word
  • Page 75 – Table 4-4. Carry Flag Manipulation Instruction
  • Page 76 – IST0, and Interrupt Servicing
  • Page 77 – RBE is automatically initialized.
  • Page 78 – Figure 4-14. Configuration of Bank Select Register
  • Page 80 – lation instructions
  • Page 81 – CHAPTER 5 EEPROM; Figure 5-1. Format of EEPROM Write Control Register; EEPROM read enable flag
  • Page 82 – Interrupt Related to EEPROM Control
  • Page 83 – EEPROM Manipulation Method
  • Page 85 – Use the following procedure to write to EEPROM.; Operating mode selection bit
  • Page 87 – Cautions on EEPROM Writing; Cautions on EEPROM writing are shown below.
  • Page 88 – CHAPTER 6 PERIPHERAL HARDWARE FUNCTION; Figure 6-1. Data Memory Address of Digital Ports
  • Page 89 – CHAPTER 6 PERIPHERAL HARDWARE FUNCTION; Table 6-1. Types and Features of Digital Ports; Port; Hardware Controlling Interrupt Function; are turned off, and the ports are set to the input mode.
  • Page 94 – when the corresponding register bit is “1”.; MBE
  • Page 95 – Figure 6-10. Format of Each Port Mode Register; Specification; Port mode register group A
  • Page 98 – the data of each pin is manipulated.
  • Page 100 – Figure 6-11. Format of Pull-up Resistor Specification Register
  • Page 101 – the data of the output latch is loaded to the internal bus.
  • Page 103 – Figure 6-14 shows the configuration of the clock generator.; Instruction execution; : System clock frequency; ) of the CPU clock is equal to one machine cycle of the instruction.
  • Page 105 – Function and operation of clock generator
  • Page 106 – CHAPTER 8 STANDBY FUNCTION
  • Page 107 – Figure 6-15. Format of Processor Clock Control Register; CPU operating mode control bits; and f
  • Page 108 – An external clock cannot be input for RC oscillation.; Cautions f; Figure 6-16. RC Oscillation External Circuit; An external clock can also be input.; Crystal/ceramic oscillation
  • Page 109 – Figure 6-18 shows incorrect examples of connecting the resonator.
  • Page 110 – (c) High alternating current close to signal line
  • Page 111 – (d) Current flowing through power line of oscillator
  • Page 112 – Table 6-5. Maximum Time Required for CPU Clock Switching
  • Page 113 – Figure 6-19. CPU Clock Switching Example; Notes
  • Page 114 – Figure 6-20. Block Diagram of Basic Interval Timer/Watchdog Timer
  • Page 116 – Figure 6-21. Format of Basic Interval Timer Mode Register; In the
  • Page 117 – To set watchdog timer function
  • Page 119 – Initial setting; Figure; indicates occurrence and detection of a program hang-up.
  • Page 120 – To use the; It is 7.81 ms when the
  • Page 121 – Caution
  • Page 122 – The; Corresponding function is not available.
  • Page 123 – Execution of the instruction; Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0.
  • Page 125 – Caution Be sure to clear bit 7 to 0 when setting data to TC2.
  • Page 126 – SEL; CP = 977 kHz when the
  • Page 127 – Be sure to clear bits 0 and 1 to 0 when setting data to TM0.; the count pulse set becomes 0 and TM0 does not operate as a timer.; Timer start command bit
  • Page 129 – This mode is used as a carrier generator mode when used in; set becomes 0 and TM0 does not operate as a timer.
  • Page 132 – Figure 6-29. Format of Timer Counter Output Enable Flag
  • Page 133 – Figure 6-30. Format of Timer Counter Control Register; No return zero flag; Be sure to clear bits 7 to 0 when setting data to TC2.
  • Page 134 – -bit programmable interval timer or counter.; to
  • Page 138 – Timer counter output enable flag; Figure 6-33. Setting of Timer Counter Output Enable Flag
  • Page 139 – frequency] selected by the mode register.; Contents of modulo register (n
  • Page 142 – The timer counter operates as follows.
  • Page 143 – Figure 6-34. Configuration When Timer Counter Operates; m : Set value of timer counter modulo register
  • Page 145 – The timer counter operates as an 8-bit PWM pulse generator.; of Timer Counter Mode Register (Channel 2)
  • Page 146 – Figure 6-36. Setting of Timer Counter Mode Register; select bits TM10 and TM11 of the time counter (channel 1) to 0.
  • Page 147 – of Timer Counter Control Register); TC2 is cleared to 00H when the internal reset signal is asserted.; Figure 6-37. Setting of Timer Counter Control Register
  • Page 149 – Figure 6-38. PWM Pulse Generator Operating Configuration; This is the IRQT2 set signal. It is only set when TMOD2 matches T2.; Figure 6-39. PWM Pulse Generator Operating Timing
  • Page 152 – Figure 6-40. Setting of Timer Counter Mode Registers
  • Page 153 – Figure 6-41. Setting of Timer Counter Control Register
  • Page 157 – Figure 6-42. Configuration When Timer Counter Operates
  • Page 158 – Set value of timer counter modulo register (TMOD2)
  • Page 162 – the format of TC2, refer to; Figure 6-30 Format of Timer Counter Control Register; Figure 6-46. Setting of Timer Counter Control Register
  • Page 163 – counter in the carrier generator mode.
  • Page 164 – Figure 6-48 shows the timing of the carrier generator operation.
  • Page 165 – Figure 6-47. Configuration in Carrier Generator Mode
  • Page 166 – Figure 6-48. Carrier Generator Operation Timing
  • Page 167 – from the pulse after the carrier clock.
  • Page 170 – and timer start command.
  • Page 173 – resolution, deviates by up
  • Page 176 – (4) Operation after changing modulo register; changing TMODn and TMOD2H.
  • Page 177 – an error that may occur when the timer is started.
  • Page 178 – hold constant the high-level period of the carrier.
  • Page 179 – carrier may not be output to the PTO2 pin as shown below.; the carrier output to the PTO2 pin may be extended as shown below.
  • Page 180 – Configuration and operation of programmable threshold port
  • Page 181 – Figure 6-49. Block Diagram of Programmable Threshold Port
  • Page 182 – memory manipulation instruction.; Bit 4 and 5 of PTHM must be set to “0”.; Comparator operation mode specification; Values in parentheses are applicable when f; Threshold voltage selection
  • Page 183 – Programmable threshold port application; Buffer
  • Page 184 – long bit length in bit units.; Figure 6-52. Format of Bit Sequential Buffer; specification of MBE and MBS.
  • Page 186 – CHAPTER 7 INTERRUPT AND TEST FUNCTIONS; Configuration of Interrupt Controller
  • Page 187 – CHAPTER 7 INTERRUPT AND TEST FUNCTIONS; Figure 7-1. Block Diagram of Interrupt Controller
  • Page 188 – Types of Interrupt Sources and Vector Table
  • Page 189 – Setting of vector table of INTBT; are stored in the vector table address at address 2n.; Setting of vector tables of INTBT and INTT0
  • Page 190 – Hardware Controlling Interrupt Function; (1) Interrupt request flag and interrupt enable flag
  • Page 191 – Table 7-2. Signals Setting Interrupt Request Flags
  • Page 192 – Figure 7-3. Interrupt Priority Select Register; Selection of higher-priority interrupts; not give high priority to any interrupt.)
  • Page 194 – Even if f
  • Page 195 – This value differs depending on the system clock frequency (f
  • Page 196 – Table 7-3. IST1 and IST0 and Interrupt Servicing Status
  • Page 197 – Interrupt Sequence; Figure 7-7. Interrupt Servicing Sequence; IST1 and 0: Interrupt status flags (bits 3 and 2 of PSW Refer to
  • Page 198 – Nesting Control of Interrupts; (1) Nesting with interrupt having high priority specified
  • Page 199 – (2) Nesting by changing interrupt status flags
  • Page 200 – Servicing of Interrupts Sharing Vector Address; Table 7-4. Identifying Interrupt Sharing Vector Address
  • Page 201 – Examples
  • Page 202 – Machine Cycles Until Interrupt Servicing; routine is executed is as follows.; Sets IRQxxx; Remarks; manipulated when an interrupt is acknowledged.
  • Page 204 – Effective Usage of Interrupts; Use the interrupt function effectively as follows.; Application of Interrupt
  • Page 205 – <2> An interrupt enable flag is set by the EI IE
  • Page 206 – to 0 and interrupts are enabled.
  • Page 207 – interrupts are disabled.
  • Page 210 – interrupt with the lower priority is held pending.
  • Page 212 – Hardware controlling test function
  • Page 213 – Figure 7-10. Block Diagram of KR4 to KR7
  • Page 214 – If a low level is input to even one of the KR
  • Page 215 – CHAPTER 8 STANDBY FUNCTION; Cautions
  • Page 216 – CHAPTER 8 STANDBY FUNCTION; Settings and Operating Statuses of Standby Mode; Table 8-1. Operating Statuses in Standby Mode
  • Page 217 – and HALT instructions respectively set bits 3 and 2 of PCC).
  • Page 218 – Releasing Standby Mode; Figure 8-1 illustrates how each mode is released.; (a) Releasing STOP mode by RESET signal, or by key return reset; PD754244: The following two times can be selected by mask option.
  • Page 221 – Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input
  • Page 222 – Operation After Release of Standby Mode; has been released. The interrupt request flag is retained.; Application of Standby Mode; Use the standby mode according to the following procedure.; on whether interrupt servicing is performed or not).
  • Page 223 – ; INT0 pin is checked twice to prevent chattering.
  • Page 225 – • INT0 and INTBT are assigned a lower priority.
  • Page 227 – Figure 9-1. Configuration of Reset Circuit; the timing of the reset operation.
  • Page 228 – CHAPTER 9 RESET FUNCTION; Figure 9-2. Reset Operation by RESET Signal
  • Page 231 – WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively.; Table 9-2. WDF and KRF Contents Corresponding to Each Signal
  • Page 232 – Figure 9-4. KRF Operation in Generating Each Signal
  • Page 233 – CHAPTER 10 MASK OPTIONS; Pin Mask Options; Releasing Standby Mode
  • Page 234 – CHAPTER 11 INSTRUCTION SET; The instruction set of the; (1) Bit manipulation instructions for various applications; Unique Instructions; This section describes the instructions unique to the
  • Page 235 – CHAPTER 11 INSTRUCTION SET
  • Page 236 – Base number adjustment instruction; or subtraction of 4-bit data into a number with any base.; (1) Base adjustment of result of addition; Occurrence of an overflow is indicated by the carry flag.; To add accumulator and memory in decimal; (2) Base adjustment of result of subtraction; of subtraction is adjusted to a number with a base of m.
  • Page 237 – Instruction Set and Operation; (1) Operand representation and description; and
  • Page 239 – (2) Conventions for explanation of operation
  • Page 241 – The value of S varies as follows.; One machine cycle is equal to one cycle of CPU clock; Figure 6-15 Processor Clock Control Register Format
  • Page 243 – Set 0 to the B register.
  • Page 245 – PCDE; BRA; Set 0 to the B register
  • Page 248 – Opcode of Each Instruction
  • Page 249 – (2) Opcode for bit manipulation addressing; *1 in the operand field indicates the following three types.
  • Page 254 – Instruction Function and Application; How to read; : This instruction can be used only in the MkI mode of the; II
  • Page 255 – Application example
  • Page 256 – the next instruction is skipped.
  • Page 260 – The address that can be specified by mem is an even address.
  • Page 261 – XA
  • Page 266 – Base number adjustment instruction
  • Page 267 – can be used in combination for base number adjustment (refer to; The carry flag is not affected.
  • Page 272 – Accumulator manipulation instructions; RORC A; NOT A
  • Page 273 – INCS reg
  • Page 275 – Carry flag manipulation instructions; SET1 CY
  • Page 276 – Memory bit manipulation instructions
  • Page 279 – BR addr
  • Page 281 – BR PCDE; BR PCXA
  • Page 282 – BR BCDE; BR BCXA; TBR addr; Assembler Package Language User’s Manual
  • Page 285 – RET; RETS; RETI
  • Page 286 – PUSH rp; rp; PUSH BS; Function; or BC), and then decrements the contents of the stack pointer.; POP BS; RBS
  • Page 287 – EI
  • Page 288 – to the register in the input mode.
  • Page 289 – HALT; Make sure that a NOP instruction follows the HALT instruction.; STOP; Make sure that a NOP instruction follows the STOP instruction.; NOP; Executes nothing but consumes 1 machine cycle.
  • Page 290 – SEL RBn; When table defined by TBR instruction is referenced; When table defined by TCALL instruction is referenced
  • Page 293 – APPENDIX A DEVELOPMENT TOOLS; combination with a device file dedicated to the model being used.; Language Processor; OS of IBM
  • Page 294 – APPENDIX A DEVELOPMENT TOOLS; Debugging Tools; This is a maintenance part.
  • Page 295 – OS of IBM PC
  • Page 296 – Development Tool Configuration
  • Page 297 – APPENDIX B ORDERING MASK ROM
  • Page 298 – APPENDIX C INSTRUCTION INDEX
  • Page 299 – APPENDIX C INSTRUCTION INDEX
  • Page 304 – APPENDIX D HARDWARE INDEX
  • Page 305 – APPENDIX D HARDWARE INDEX
  • Page 306 – APPENDIX E REVISION HISTORY
Loading the manual

User’s Manual

Printed in Japan

µ

PD754144, 754244

4-Bit Single-Chip Microcontrollers

µ

PD754144

µ

PD754244

Document No. U10676EJ3V0UM00 (3rd edition)
Date Published November 2002 N CP(K)

1997

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Summary

Page 3 - EEPROM is a trademark of NEC Electronics Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.

3 User’s Manual U10676EJ3V0UM EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. T...

Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .

4 User’s Manual U10676EJ3V0UM These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country.Diversion contrary to the law of that country is prohibited. T h e i n f o r m a t i o n i n t h i s d o c u m e n t i s c u r r...

Page 5 - Regional Information; Device availability; NEC Electronics Hong Kong Ltd.

5 User’s Manual U10676EJ3V0UM Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power ...

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